RTL simulation on CPUs remains a persistent bottleneck in hardware design. State-of-the-art simulators embed the circuit directly into the simulation binary, resulting in long compilation times and execution that is fundamentally CPU frontend-bound, with severe instruction-cache pressure. This work proposes RTeAAL Sim, which reformulates RTL simulation as a sparse tensor algebra problem. By representing RTL circuits as tensors and simulation as a sparse tensor algebra kernel, RTeAAL Sim decouples simulation behavior from binary size and makes RTL simulation amenable to well-studied tensor algebra optimizations. We demonstrate that a prototype of our tensor-based simulator, even with a subset of these optimizations, already mitigates the compilation overhead and frontend pressure and achieves performance competitive with the highly optimized Verilator simulator across multiple CPUs and ISAs.
@article{arxiv.2601.18140,
title = {RTeAAL Sim: Using Tensor Algebra to Represent and Accelerate RTL Simulation (Extended Version)},
author = {Yan Zhu and Boru Chen and Christopher W. Fletcher and Nandeeka Nayak},
journal= {arXiv preprint arXiv:2601.18140},
year = {2026}
}