The FPGA overlay architectures have been mainly proposed to improve design productivity, circuit portability and system debugging. In this paper, we address the use of overlay architectures for building fault tolerant SRAM-based FPGA systems and discuss the main features and design challenges of a reliability-aware overlay architecture.
@article{arxiv.1606.06452,
title = {Reliability-Aware Overlay Architectures for FPGAs: Features and Design Challenges},
author = {Mihalis Psarakis},
journal= {arXiv preprint arXiv:1606.06452},
year = {2016}
}
Comments
Presented at 2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016) arXiv:1605.08149