This paper presents PRIMAL, a processing-in-memory (PIM) based large language model (LLM) inference accelerator with low-rank adaptation (LoRA). PRIMAL integrates heterogeneous PIM processing elements (PEs), interconnected by 2D-mesh inter-PE computational network (IPCN). A novel SRAM reprogramming and power gating (SRPG) scheme enables pipelined LoRA updates and sub-linear power scaling by overlapping reconfiguration with computation and gating idle resources. PRIMAL employs optimized spatial mapping and dataflow orchestration to minimize communication overhead, and achieves 1.5× throughput and 25× energy efficiency over NVIDIA H100 with LoRA rank 8 (Q,V) on Llama-13B.
@article{arxiv.2601.13628,
title = {PRIMAL: Processing-In-Memory Based Low-Rank Adaptation for LLM Inference Accelerator},
author = {Yue Jiet Chong and Yimin Wang and Zhen Wu and Xuanyao Fong},
journal= {arXiv preprint arXiv:2601.13628},
year = {2026}
}
Comments
Accepted to 2026 IEEE International Symposium on Circuits and Systems (ISCAS'26)