Per-Row Activation Counting (PRAC), a DRAM read disturbance mitigation method, modifies key DRAM timing parameters, reportedly causing significant performance overheads in simulator-based studies. However, given known discrepancies between simulators and real hardware, real-machine experiments are vital for accurate PRAC performance estimation. We present the first real-machine performance analysis of PRAC. After verifying timing modifications on the latest CPUs using microbenchmarks, our analysis shows that PRAC's average and maximum overheads are just 1.06% and 3.28% for the SPEC CPU2017 workloads -- up to 9.15x lower than simulator-based reports. Further, we show that the close page policy minimizes this overhead by effectively hiding the elongated DRAM row precharge operations due to PRAC from the critical path.
@article{arxiv.2507.05556,
title = {Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads},
author = {Jumin Kim and Seungmin Baek and Minbok Wi and Hwayong Nam and Michael Jaemin Kim and Sukhan Lee and Kyomin Sohn and Jung Ho Ahn},
journal= {arXiv preprint arXiv:2507.05556},
year = {2025}
}
Comments
5 pages, 4 figures, modified on top of the IEEE Computer Architecture Letters