Modeling and Energy Optimization of LDPC Decoder Circuits with Timing Violations
Abstract
This paper proposes a "quasi-synchronous" design approach for signal processing circuits, in which timing violations are permitted, but without the need for a hardware compensation mechanism. The case of a low-density parity-check (LDPC) decoder is studied, and a method for accurately modeling the effect of timing violations at a high level of abstraction is presented. The error-correction performance of code ensembles is then evaluated using density evolution while taking into account the effect of timing faults. Following this, several quasi-synchronous LDPC decoder circuits based on the offset min-sum algorithm are optimized, providing a 23%-40% reduction in energy consumption or energy-delay product, while achieving the same performance and occupying the same area as conventional synchronous circuits.
Cite
@article{arxiv.1503.03880,
title = {Modeling and Energy Optimization of LDPC Decoder Circuits with Timing Violations},
author = {François Leduc-Primeau and Frank R. Kschischang and Warren J. Gross},
journal= {arXiv preprint arXiv:1503.03880},
year = {2017}
}
Comments
To appear in IEEE Transactions on Communications