We present a construction for circuits with low gate count and depth, implementing three- and four-body Pauli-Z product operators as they appear in the form of plaquette-shaped constraints in QAOA when using the parity mapping. The circuits can be implemented on any quantum device with nearest-neighbor connectivity on a square-lattice, using only one gate type and one orientation of two-qubit gates at a time. We find an upper bound for the circuit depth which is independent of the system size. The procedure is readily adjustable to hardware-specific restrictions, such as a minimum required spatial distance between simultaneously executed gates, or gates only being simultaneously executable within a subset of all the qubits, for example a single line.
@article{arxiv.2211.11287,
title = {Low-depth Circuit Implementation of Parity Constraints for Quantum Optimization},
author = {Josua Unger and Anette Messinger and Benjamin E. Niehoff and Michael Fellner and Wolfgang Lechner},
journal= {arXiv preprint arXiv:2211.11287},
year = {2024}
}