In chip design planning, obtaining reliable performance and power forecasts for various design options is of critical importance. Traditionally, this involves using system-level models, which often lack accuracy, or trial synthesis, which is both labor-intensive and time-consuming. We introduce a new methodology, called Lorecast, which accepts English prompts as input to rapidly generate layout-aware performance and power estimates. This approach bypasses the need for HDL code development and synthesis, making it both fast and user-friendly. Experimental results demonstrate that Lorecast achieves accuracy within a few percent of error compared to post-layout analysis, while significantly reducing turnaround time.
@article{arxiv.2503.11662,
title = {Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language},
author = {Runzhi Wang and Prianka Sengupta and Cristhian Roman-Vicharra and Yiran Chen and Jiang Hu},
journal= {arXiv preprint arXiv:2503.11662},
year = {2025}
}