Co-developing scientific algorithms and hardware accelerators requires domain-specific knowledge and large engineering resources. This leads to a slow development pace and high project complexity, which creates a barrier to entry that is too high for the majority of developers to overcome. We are developing a reusable end-to-end compiler toolchain for the Julia language entirely built on permissively-licensed open-source projects. This unifies accelerator and algorithm development by automatically synthesising Julia source code into high-performance Verilog.
@article{arxiv.2503.09463,
title = {Hardware.jl - An MLIR-based Julia HLS Flow (Work in Progress)},
author = {Benedict Short and Ian McInerney and John Wickerson},
journal= {arXiv preprint arXiv:2503.09463},
year = {2025}
}
Comments
Accepted for presentation at the 5th Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE'25), March 30, 2025, Rotterdam, Netherlands