Gate--Level Statistical Timing Analysis: Exact Solutions, Approximations and Algorithms
Systems and Control
2024-01-09 v1 Hardware Architecture
Systems and Control
Abstract
In this paper, the Statistical Static Timing Analysis (SSTA) is considered within the block--based approach. The statistical model of the logic gate delay propagation is systematically studied and the exact analytical solution is obtained, which is strongly non-Gaussian. The procedure of handling such (non-Gaussian) distributions is described and the corresponding algorithm for the critical path delay is outlined. Finally, the proposed approach is tested and compared with Monte Carlo simulations.
Keywords
Cite
@article{arxiv.2401.03588,
title = {Gate--Level Statistical Timing Analysis: Exact Solutions, Approximations and Algorithms},
author = {Dmytro Mishagli and Eugene Koskin and Elena Blokhina},
journal= {arXiv preprint arXiv:2401.03588},
year = {2024}
}