We introduce ForgeEDA, an open-source comprehensive circuit dataset across various categories. ForgeEDA includes diverse circuit representations such as Register Transfer Level (RTL) code, Post-mapping (PM) netlists, And-Inverter Graphs (AIGs), and placed netlists, enabling comprehensive analysis and development. We demonstrate ForgeEDA's utility by benchmarking state-of-the-art EDA algorithms on critical tasks such as Power, Performance, and Area (PPA) optimization, highlighting its ability to expose performance gaps and drive advancements. Additionally, ForgeEDA's scale and diversity facilitate the training of AI models for EDA tasks, demonstrating its potential to improve model performance and generalization. By addressing limitations in existing datasets, ForgeEDA aims to catalyze breakthroughs in modern IC design and support the next generation of innovations in EDA.
@article{arxiv.2505.02016,
title = {ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA},
author = {Zhengyuan Shi and Zeju Li and Chengyu Ma and Yunhao Zhou and Ziyang Zheng and Jiawei Liu and Hongyang Pan and Lingfeng Zhou and Kezhi Li and Jiaying Zhu and Lingwei Yan and Zhiqiang He and Chenhao Xue and Wentao Jiang and Fan Yang and Guangyu Sun and Xiaoyan Yang and Gang Chen and Chuan Shi and Zhufei Chu and Jun Yang and Qiang Xu},
journal= {arXiv preprint arXiv:2505.02016},
year = {2025}
}