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Floating-Point Multiply-Add with Approximate Normalization for Low-Cost Matrix Engines

Hardware Architecture 2024-08-23 v1

Abstract

The widespread adoption of machine learning algorithms necessitates hardware acceleration to ensure efficient performance. This acceleration relies on custom matrix engines that operate on full or reduced-precision floating-point arithmetic. However, conventional floating-point implementations can be power hungry. This paper proposes a method to improve the energy efficiency of the matrix engines used in machine learning algorithm acceleration. Our approach leverages approximate normalization within the floating-point multiply-add units as a means to reduce their hardware complexity, without sacrificing overall machine-learning model accuracy. Hardware synthesis results show that this technique reduces area and power consumption roughly by 16% and 13% on average for Bfloat16 format. Also, the error introduced in transformer model accuracy is 1% on average, for the most efficient configuration of the proposed approach.

Keywords

Cite

@article{arxiv.2408.11997,
  title  = {Floating-Point Multiply-Add with Approximate Normalization for Low-Cost Matrix Engines},
  author = {Kosmas Alexandridis and Christodoulos Peltekis and Dionysios Filippas and Giorgos Dimitrakopoulos},
  journal= {arXiv preprint arXiv:2408.11997},
  year   = {2024}
}
R2 v1 2026-06-28T18:20:08.660Z