Evaluation of Single-Chip, Real-Time Tomographic Data Processing on FPGA - SoC Devices
Abstract
A novel approach to tomographic data processing has been developed and evaluated using the Jagiellonian PET (J-PET) scanner as an example. We propose a system in which there is no need for powerful, local to the scanner processing facility, capable to reconstruct images on the fly. Instead we introduce a Field Programmable Gate Array (FPGA) System-on-Chip (SoC) platform connected directly to data streams coming from the scanner, which can perform event building, filtering, coincidence search and Region-Of-Response (ROR) reconstruction by the programmable logic and visualization by the integrated processors. The platform significantly reduces data volume converting raw data to a list-mode representation, while generating visualization on the fly.
Cite
@article{arxiv.1807.10754,
title = {Evaluation of Single-Chip, Real-Time Tomographic Data Processing on FPGA - SoC Devices},
author = {G. Korcyl and P. Białas and C. Curceanu and E. Czerwiński and K. Dulski and B. Flak and A. Gajos and B. Głowacz and M. Gorgol and B. C. Hiesmayr and B. Jasińska and K. Kacprzak and M. Kajetanowicz and D. Kisielewska and P. Kowalski and T. Kozik and N. Krawczyk and W. Krzemień and E. Kubicz and M. Mohammed and Sz. Niedźwiecki and M. Pawlik-Niedźwiecka and M. Pałka and L. Raczyński and P. Rajda and Z. Rudy and P. Salabura and N. G. Sharma and S. Sharma and R. Y. Shopa and M. Skurzok and M. Silarski and P. Strzempek and A. Wieczorek and W. Wiślicki and R. Zaleski and B. Zgardzińska and M. Zieliński and P. Moskal},
journal= {arXiv preprint arXiv:1807.10754},
year = {2018}
}
Comments
IEEE Transactions on Medical Imaging, 17 May 2018