English

DMR-based Technique for Fault Tolerant AES S-box Architecture

Hardware Architecture 2020-09-14 v1

Abstract

This paper presents a high-throughput fault-resilient hardware implementation of AES S-box, called HFS-box. If a transient natural or even malicious fault in each pipeline stage is detected, the corresponding error signal becomes high and as a result, the control unit holds the output of our proposed DMR voter till the fault effect disappears. The proposed low-cost HFS-box provides a high capability of fault-tolerant against transient faults with any duration by putting low area overhead, i.e. 137%, and low throughput degradation, i.e. 11.3%, on the original implementation.

Keywords

Cite

@article{arxiv.2009.05329,
  title  = {DMR-based Technique for Fault Tolerant AES S-box Architecture},
  author = {Mahdi Taheri and Saeideh Sheikhpour and Mohammad Saeed Ansari and Ali Mahani},
  journal= {arXiv preprint arXiv:2009.05329},
  year   = {2020}
}
R2 v1 2026-06-23T18:28:08.461Z