Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor
Abstract
In this paper, we introduce the design and verification frameworks for developing a fully-functional emerging ternary processor. Based on the existing compiling environments for binary processors, for the given ternary instructions, the software-level framework provides an efficient way to convert the given programs to the ternary assembly codes. We also present a hardware-level framework to rapidly evaluate the performance of a ternary processor implemented in arbitrary design technology. As a case study, the fully-functional 9-trit advanced RISC-based ternary (ART-9) core is newly developed by using the proposed frameworks. Utilizing 24 custom ternary instructions, the 5-stage ART-9 prototype architecture is successfully verified by a number of test programs including dhrystone benchmark in a ternary domain, achieving the processing efficiency of 57.8 DMIPS/W and 3.06 x 10^6 DMIPS/W in the FPGA-level ternary-logic emulations and the emerging CNTFET ternary gates, respectively.
Cite
@article{arxiv.2111.07584,
title = {Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor},
author = {Dongyun Kam and Jung Gyu Min and Jongho Yoon and Sunmean Kim and Seokhyeong Kang and Youngjoo Lee},
journal= {arXiv preprint arXiv:2111.07584},
year = {2021}
}
Comments
Accepted to DATE 2022