English

Demonstrating BrainScaleS-2 Inter-Chip Pulse-Communication using EXTOLL

Hardware Architecture 2022-03-04 v2 Neural and Evolutionary Computing Networking and Internet Architecture

Abstract

The BrainScaleS-2 (BSS-2) Neuromorphic Computing System currently consists of multiple single-chip setups, which are connected to a compute cluster via Gigabit-Ethernet network technology. This is convenient for small experiments, where the neural networks fit into a single chip. When modeling networks of larger size, neurons have to be connected across chip boundaries. We implement these connections for BSS-2 using the EXTOLL networking technology. This provides high bandwidths and low latencies, as well as high message rates. Here, we describe the targeted pulse-routing implementation and required extensions to the BSS-2 software stack. We as well demonstrate feed-forward pulse-routing on BSS-2 using a scaled-down version without temporal merging.

Cite

@article{arxiv.2202.12122,
  title  = {Demonstrating BrainScaleS-2 Inter-Chip Pulse-Communication using EXTOLL},
  author = {Tobias Thommes and Sven Bordukat and Andreas Grübl and Vitali Karasenko and Eric Müller and Johannes Schemmel},
  journal= {arXiv preprint arXiv:2202.12122},
  year   = {2022}
}

Comments

3 pages, 2 figures, submitted to the Neuro Inspired Computational Elements 2022 (NICE'2022) conference, accepted and presented as a lightning-talk in March 2022; 1st replacement: version to be published in the conference proceedings

R2 v1 2026-06-24T09:52:33.077Z