With the rise of Deep Learning (DL), our world braces for AI in every edge device, creating an urgent need for edge-AI SoCs. This SoC hardware needs to support high throughput, reliable and secure AI processing at Ultra Low Power (ULP), with a very short time to market. With its strong legacy in edge solutions and open processing platforms, the EU is well-positioned to become a leader in this SoC market. However, this requires AI edge processing to become at least 100 times more energy-efficient, while offering sufficient flexibility and scalability to deal with AI as a fast-moving target. Since the design space of these complex SoCs is huge, advanced tooling is needed to make their design tractable. The CONVOLVE project (currently in Inital stage) addresses these roadblocks. It takes a holistic approach with innovations at all levels of the design hierarchy. Starting with an overview of SOTA DL processing support and our project methodology, this paper presents 8 important design choices largely impacting the energy efficiency and flexibility of DL hardware. Finding good solutions is key to making smart-edge computing a reality.
@article{arxiv.2212.00873,
title = {CONVOLVE: Smart and seamless design of smart edge processors},
author = {M. Gomony and F. Putter and A. Gebregiorgis and G. Paulin and L. Mei and V. Jain and S. Hamdioui and V. Sanchez and T. Grosser and M. Geilen and M. Verhelst and F. Zenke and F. Gurkaynak and B. Bruin and S. Stuijk and S. Davidson and S. De and M. Ghogho and A. Jimborean and S. Eissa and L. Benini and D. Soudris and R. Bishnoi and S. Ainsworth and F. Corradi and O. Karrakchou and T. Güneysu and H. Corporaal},
journal= {arXiv preprint arXiv:2212.00873},
year = {2023}
}