English

BETA: Binarized Energy-Efficient Transformer Accelerator at the Edge

Hardware Architecture 2024-07-16 v2 Artificial Intelligence

Abstract

Existing binary Transformers are promising in edge deployment due to their compact model size, low computational complexity, and considerable inference accuracy. However, deploying binary Transformers faces challenges on prior processors due to inefficient execution of quantized matrix multiplication (QMM) and the energy consumption overhead caused by multi-precision activations. To tackle the challenges above, we first develop a computation flow abstraction method for binary Transformers to improve QMM execution efficiency by optimizing the computation order. Furthermore, a binarized energy-efficient Transformer accelerator, namely BETA, is proposed to boost the efficient deployment at the edge. Notably, BETA features a configurable QMM engine, accommodating diverse activation precisions of binary Transformers and offering high-parallelism and high-speed for QMMs with impressive energy efficiency. Experimental results evaluated on ZCU102 FPGA show BETA achieves an average energy efficiency of 174 GOPS/W, which is 1.76~21.92x higher than prior FPGA-based accelerators, showing BETA's good potential for edge Transformer acceleration.

Keywords

Cite

@article{arxiv.2401.11851,
  title  = {BETA: Binarized Energy-Efficient Transformer Accelerator at the Edge},
  author = {Yuhao Ji and Chao Fang and Zhongfeng Wang},
  journal= {arXiv preprint arXiv:2401.11851},
  year   = {2024}
}

Comments

This paper is accepted by 2024 IEEE International Symposium on Circuits and Systems (ISCAS 2024)

R2 v1 2026-06-28T14:23:22.758Z