There has been abundant research on the development of Approximate Circuits (ACs) for ASICs. However, previous studies have illustrated that ASIC-based ACs offer asymmetrical gains in FPGA-based accelerators. Therefore, an AC that might be pareto-optimal for ASICs might not be pareto-optimal for FPGAs. In this work, we present the ApproxFPGAs methodology that uses machine learning models to reduce the exploration time for analyzing the state-of-the-art ASIC-based ACs to determine the set of pareto-optimal FPGA-based ACs. We also perform a case-study to illustrate the benefits obtained by deploying these pareto-optimal FPGA-based ACs in a state-of-the-art automation framework to systematically generate pareto-optimal approximate accelerators that can be deployed in FPGA-based systems to achieve high performance or low-power consumption.
@article{arxiv.2004.10502,
title = {ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems},
author = {Bharath Srinivas Prabakaran and Vojtech Mrazek and Zdenek Vasicek and Lukas Sekanina and Muhammad Shafique},
journal= {arXiv preprint arXiv:2004.10502},
year = {2020}
}
Comments
Accepted for Publication at the 57th Design Automation Conference (DAC), July 2020, San Francisco, CA, USA