English

Apparate: Evading Memory Hierarchy with GodSpeed Wireless-on-Chip

Hardware Architecture 2024-06-12 v1 Emerging Technologies

Abstract

The rapid advancements in memory systems, CPU technology, and emerging technologies herald a transformative potential in computing, promising to revolutionize memory hierarchies. Innovations in DDR memory are delivering unprecedented bandwidth, while advancements in on-chip wireless technology are reducing size and increasing speed. The introduction of godspeed wireless transceivers on chip, alongside near high-speed DRAM, is poised to directly facilitate memory requests. This integration suggests the potential for eliminating traditional memory hierarchies, offering a new paradigm in computing efficiency and speed. These developments indicate a near-future where computing systems are significantly more responsive and powerful, leveraging direct, high-speed memory access mechanisms.

Keywords

Cite

@article{arxiv.2406.06536,
  title  = {Apparate: Evading Memory Hierarchy with GodSpeed Wireless-on-Chip},
  author = {Nitesh Narayana GS and Abhijit Das},
  journal= {arXiv preprint arXiv:2406.06536},
  year   = {2024}
}

Comments

ASPLOS 2024, Wild and Crazy Ideas (WACI) session

R2 v1 2026-06-28T17:00:04.589Z