An FPGA-based readout chip emulator for the CMS ETL detector upgrade

L. Zhang; C. Edwards; D. Gong; X. Huang; J. Lee; C. Liu; T. Liu; T. Liu; J. Olsen; Q. Sun; J. Wu; J. Ye; W Zhang

doi:10.1088/1748-0221/18/02/C02031

An FPGA-based readout chip emulator for the CMS ETL detector upgrade

Instrumentation and Detectors 2023-03-01 v1

Authors: L. Zhang , C. Edwards , D. Gong , X. Huang , J. Lee , C. Liu , T. Liu , T. Liu , J. Olsen , Q. Sun , J. Wu , J. Ye , W Zhang

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Abstract

We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented and verified. The emulator board is being used for the ETROC digital design verification and system development.

Keywords

detector readout electronics

Cite

@article{arxiv.2302.01548,
  title  = {An FPGA-based readout chip emulator for the CMS ETL detector upgrade},
  author = {L. Zhang and C. Edwards and D. Gong and X. Huang and J. Lee and C. Liu and T. Liu and T. Liu and J. Olsen and Q. Sun and J. Wu and J. Ye and W Zhang},
  journal= {arXiv preprint arXiv:2302.01548},
  year   = {2023}
}

Comments

8 pages, 4 figures

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