A Technique for Efficiently Managing SRAM-NVM Hybrid Cache

Sparsh Mittal

A Technique for Efficiently Managing SRAM-NVM Hybrid Cache

Hardware Architecture 2013-11-04 v1

Authors: Sparsh Mittal

Abstract

In this paper, we present a SRAM-PCM hybrid cache design, along with a cache replacement policy, named dead fast block (DFB) to manage the hybrid cache. This design aims to leverage the best features of both SRAM and PCM devices. Compared to a PCM-only cache, the hybrid cache with DFB policy provides superior results on all relevant evaluation metrics, viz. cache lifetime, performance and energy efficiency. Also, use of DFB policy for managing the hybrid cache provides better results compared to LRU replacement policy on all the evaluation metrics.

Keywords

memory hierarchy processing-in-memory

Cite

@article{arxiv.1311.0170,
  title  = {A Technique for Efficiently Managing SRAM-NVM Hybrid Cache},
  author = {Sparsh Mittal},
  journal= {arXiv preprint arXiv:1311.0170},
  year   = {2013}
}

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