We have developed a novel compiler called the Multiple-Architecture Compiler for Advanced Computing Hardware (MACH) designed specifically for massively-parallel, spatial, dataflow architectures like the Wafer Scale Engine. Additionally, MACH can execute code on traditional unified-memory devices. MACH addresses the complexities in compiling for spatial architectures through a conceptual Virtual Machine, a flexible domain-specific language, and a compiler that can lower high-level languages to machine-specific code in compliance with the Virtual Machine concept. While MACH is designed to be operable on several architectures and provide the flexibility for several standard and user-defined data mappings, we introduce the concept with dense tensor examples from NumPy and show lowering to the Wafer Scale Engine by targeting Cerebras' hardware specific languages.
@article{arxiv.2506.15875,
title = {A System Level Compiler for Massively-Parallel, Spatial, Dataflow Architectures},
author = {Dirk Van Essendelft and Patrick Wingo and Terry Jordan and Ryan Smith and Wissam Saidi},
journal= {arXiv preprint arXiv:2506.15875},
year = {2025}
}