A Real Time Super Resolution Accelerator with Tilted Layer Fusion
Hardware Architecture
2022-05-10 v1 Machine Learning
Image and Video Processing
Abstract
Deep learning based superresolution achieves high-quality results, but its heavy computational workload, large buffer, and high external memory bandwidth inhibit its usage in mobile devices. To solve the above issues, this paper proposes a real-time hardware accelerator with the tilted layer fusion method that reduces the external DRAM bandwidth by 92\% and just needs 102KB on-chip memory. The design implemented with a 40nm CMOS process achieves 1920x1080@60fps throughput with 544.3K gate count when running at 600MHz; it has higher throughput and lower area cost than previous designs.
Cite
@article{arxiv.2205.03997,
title = {A Real Time Super Resolution Accelerator with Tilted Layer Fusion},
author = {An-Jung Huang and Kai-Chieh Hsu and Tian-Sheuan Chang},
journal= {arXiv preprint arXiv:2205.03997},
year = {2022}
}
Comments
5 pages, 6 figures, published in ISCAS 2022