A compact butterfly-style silicon photonic-electronic neural chip for hardware-efficient deep learning
Abstract
The optical neural network (ONN) is a promising hardware platform for next-generation neurocomputing due to its high parallelism, low latency, and low energy consumption. Previous ONN architectures are mainly designed for general matrix multiplication (GEMM), leading to unnecessarily large area cost and high control complexity. Here, we move beyond classical GEMM-based ONNs and propose an optical subspace neural network (OSNN) architecture, which trades the universality of weight representation for lower optical component usage, area cost, and energy consumption. We devise a butterfly-style photonic-electronic neural chip to implement our OSNN with up to 7x fewer trainable optical components compared to GEMM-based ONNs. Additionally, a hardware-aware training framework is provided to minimize the required device programming precision, lessen the chip area, and boost the noise robustness. We experimentally demonstrate the utility of our neural chip in practical image recognition tasks, showing that a measured accuracy of 94.16% can be achieved in hand-written digit recognition tasks with 3-bit weight programming precision.
Cite
@article{arxiv.2111.06705,
title = {A compact butterfly-style silicon photonic-electronic neural chip for hardware-efficient deep learning},
author = {Chenghao Feng and Jiaqi Gu and Hanqing Zhu and Zhoufeng Ying and Zheng Zhao and David Z. Pan and Ray T. Chen},
journal= {arXiv preprint arXiv:2111.06705},
year = {2022}
}
Comments
17 pages,5 figures