Related papers: Development of an ASD IC for the Micro Pixel Chamb…

A single channel 1.5GS/s 8-bit pipelined-SAR ADC utilizes a novel output level shifting (OLS) settling technique to reduce the power and enable low-voltage operation of the dynamic residue amplifier. The ADC consists of a 4-bit first stage…

In this paper, we propose an analog pixel differencing circuit for differentiating pixels between frames directly from CMOS pixels. The analog information processing at sensor is a topic of growing appeal to develop edge AI devices. The…

Conventional analog and mixed-signal (AMS) circuit designs heavily rely on manual effort, which is time-consuming and labor-intensive. This paper presents a fully automated design methodology for Successive Approximation Register (SAR)…

In this work, a new method for designing an analog circuit for deep sub-micron CMOS fabrication processes is proposed. The proposed method leverages the regression algorithms with the transistor circuit model to size a transistor in 0.18 um…

Switched capacitor arrays (SCA) ASICs are becoming more and more popular for the readout of detector signals, since the sampling frequency of typically several gigasamples per second allows excellent pile-up rejection and time measurements.…

We present a programmable 16 channel, mixed signal, low power readout ASIC, having the project historically named Gigasample Recorder of Analog waveforms from a PHotodetector (GRAPH). It is designed to read large aperture single photon…

An X-ray detector will be presented that is the combination of a segmented ionization chamber featuring one-dimensional spatial resolution integrated with an intelligent ADC front-end, multi DSP processing and embedded PC platform. This…

An eight chip InGrid module has been tested as readout of a prototype time projection chamber. The construction of the modules as well as first preliminary results are presented. The InGrids, a Micromegas like amplification structure with a…

Dynamic comparators are the core of high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. Most of the dynamic comparators attain high-speed operation only for sufficiently high input difference…

XRPIX is the monolithic X-ray SOI (silicon-on-insulator) pixel detector, which has a time resolution better than 10 $\rm{\mu}$s as well as a high detection efficiency for X-rays above 10 keV. XRPIX is planned to be installed on future X-ray…

Deep-learning accelerators are increasingly in demand; however, their performance is constrained by the size of the feature map, leading to high bandwidth requirements and large buffer sizes. We propose an adaptive scale feature map…

The ubiquitous use of sensing and signal processing is increasing exponentially with the advance of the Internet of Everything (IoE). In this context, the design of every time more power efficient sensor nodes is a must. Within these nodes,…

We report on the development and characterization of the low-noise, low power, mixed analog-digital SIRIUS ASICs for both the LAD and WFM X-ray instruments of LOFT. The ASICs we developed are reading out large area silicon drift detectors…

The detector of TRopIcal DEep-sea Neutrino Telescope (TRIDENT) will use large-area silicon photomultiplier (SiPM) arrays combined with photomultiplier tubes to boost photon detection efficiency and pointing capability. An…

An ADC is used to convert analog signals into binary signals. Compared with many other types of ADCs, flash converters are incredibly quick. A typical Flash ADC consists of 2n resistors, 2n-1 op-amp comparators, and an encoder which…

This work presents a custom analog front-end card designed for the read-out of PMTs coupled to lanthanum bromide scintillators. It integrates 16 discrete analog constant fraction discriminators (CFDs) on a compact 12x10 cm board, providing…

For experiments at the European X-Ray Free-Electron Laser (XFEL) the Adaptive Gain Integrating Pixel Detector (AGIPD) is under development. The particular requirements for the detector are a high dynamic range of 0, 1 - to more than 10E4…

This paper presents a low-power 10-bit 130-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 90 nm CMOS process. The proposed asynchronous ADC consists of a comparator, SAR logic block and two control blocks…

This paper reports on the spatial and temporal resolutions of an RSD 450 microns pitch pixels array measured at the DESY test beam facility. RSDs, Resistive Silicon Detectors, also known as AC-LGAD, achieve excellent position and temporal…

The SALSA chip is a future readout ASIC foreseen for the MPGD detectors, developed in the framework of the EIC collider project, to equip the MPGD trackers of the EPIC experiment. It is designed to be versatile, to be adapted to other…