Related papers: The Data Acquisition System Based on PMC Bus
Processing-in-memory (PIM) architectures bring computation closer to data, reducing the processor-memory transfer bottleneck in traditional processor-centric designs. Novel hardware solutions, such as UPMEM's in-memory processing…
In caching system, it is desirable to design a coded caching scheme with the transmission load $R$ and subpacketization $F$ as small as possible, in order to improve efficiency of transmission in the peak traffic times and to decrease…
Mobile Edge Computing (MEC) assisted by Unmanned Aerial Vehicle (UAV) has been widely investigated as a promising system for future Internet-of-Things (IoT) networks. In this context, delay-sensitive tasks of IoT devices may either be…
In this paper, we describe a modular data acquisition system developed as the foundation of a cosmic ray detector network. Each detector setup (henceforth referred as a station) is composed of an independent hardware device that can be…
One of the outstanding challenges in contemporary science and technology is building a quantum computer that is useful in applications. By starting from an estimate of the algorithm success rate, we can explicitly connect gate fidelity to…
A novel deep neural network (DNN) architecture is proposed wherein the filtering and linear transform are realized solely with product quantization (PQ). This results in a natural implementation via content addressable memory (CAM), which…
The Message Queue (MQ) architecture is an asynchronous communication scheme that provides an attractive solution for certain scenarios in a distributed computing model. The introduction of MQ as an intermediate component in-between the…
On superconducting architectures, the state of a qubit is manipulated by using microwave pulses. Typically, the pulses are stored in the waveform memory and then streamed to the Digital-to-Analog Converter (DAC) to synthesize the gate…
Transformers face scalability challenges due to the quadratic cost of attention, which involves dense similarity computations between queries and keys. We propose CAMformer, a novel accelerator that reinterprets attention as an associative…
The integrated low-level trigger and data acquisition (TDAQ) system of the NA62 experiment at CERN is described. The requirements of a large and fast data reduction in a high-rate environment for a medium-scale, distributed ensemble of many…
Three-dimensional (3D)-stacking technology, which enables the integration of DRAM and logic dies, offers high bandwidth and low energy consumption. This technology also empowers new memory designs for executing tasks not traditionally…
We are developing DAQ for Si-pixel detectors by using a Slicon-On-Insulator (SOI) technology. This DAQ consists of firmware works on SEABAS (Soi EvAluation BoArd with Sitcp) DAQ board and software works on PC. We have been working on the…
Quantum computers hold great promise for accelerating computationally challenging algorithms on noisy intermediate-scale quantum (NISQ) devices in the upcoming years. Much attention of the current research is directed to algorithmic…
Quantum systems are inherently dissipation-less, making them excellent candidates even for classical information processing. We propose to use an array of large-spin quantum magnets for realizing a device which has two modes of operation:…
Quantum computing promises speedup of classical algorithms in the long term. Current hardware is unable to support this goal and programs must be efficiently compiled to use of the devices through reduction of qubits used, gate count and…
We propose an architecture for realizing quantum information transfer (QIT). In this architecture, a LC circuit is used to induce the necessary interaction between flux qubits, each magnetically coupling to a nitrogen-vacancy center…
Quantum random access memory (QRAM) enables efficient classical data access for quantum computers -- a prerequisite for many quantum algorithms to achieve quantum speedup. Despite various proposals, the experimental realization of QRAM…
Distributed Quantum Computing (DQC) enables scalability by interconnecting multiple QPUs. Among various DQC implementations, quantum data centers (QDCs), which utilize reconfigurable optical switch networks to link QPUs across different…
The implementation of uplink HARQ in a Cloud- Radio Access Network RAN (C-RAN) architecture is constrained by the two-way latency on the fronthaul links connecting the Remote Radio Heads (RRHs) with the Baseband Units (BBUs) that perform…
With the proposition to install a large number of phasor measurement units (PMUs) in the future power grid, it is essential to provide robust communications infrastructure for phasor data across the network. We make progress in this…