Related papers: Front End CAMAC Controller for SLAC Control System
This paper focuses on communication, radar search, and tracking task scheduling in multi-cell integrated sensing and communication (ISAC) networks under quality-of-service constraints. We propose a medium access control framework that…
The scaling up of trapped-ion quantum processors based on the quantum charge-coupled device (QCCD) architecture is difficult owing to the extensive electronics and high-density wiring required to control numerous trap electrodes. In…
In 1995 a 9SDH-2 Pelletron from NEC was installed at IFUNAM (Instituto de Fisica, Universidad Nacional Autonoma de Mexico). Two beam lines have been operational since then and two new lines have been built. In order to perform the planned…
In this brief, a model-free adaptive predictive control (MFAPC) is proposed. It outperforms the current model-free adaptive control (MFAC) for not only solving the time delay problem in multiple-input multiple-output (MIMO) systems but also…
Many large accelerator facilities have adopted the open-source EPICS software as the quasi-industry standard for control systems. They typically have access to their own electronics laboratory and dedicated personnel for control system…
Computer-based supervisory control and data acquisition (SCADA) systems have evolved over the past four decades, from standalone, compartmentalized operations into networked architectures that communicate across large distances. There is an…
The rapid advancements in AI, scientific computing, and high-performance computing (HPC) have driven the need for versatile and efficient hardware accelerators. Existing tools like SCALE-Sim v2 provide valuable cycle-accurate simulations…
Cyber-physical systems such as microgrids consist of interconnected components, localized power systems, and distributed energy resources with clearly defined electrical boundaries. They can function independently but can also work in…
This correspondence paper studies a network integrated sensing and communication (ISAC) system that unifies the interference channel for communication and distributed radar sensing. In this system, a set of distributed ISAC transmitters…
This paper presents a hierarchical control scheme for interconnected linear systems. At the higher layer of the control structure a robust centralized Model Predictive Control (MPC) algorithm based on a reduced order dynamic model of the…
Solid-state qubits have recently advanced to the level that enables them, in-principle, to be scaled-up into fault-tolerant quantum computers. As these physical qubits continue to advance, meeting the challenge of realising a quantum…
The dense concentration of low-altitude, slow-speed, and small-size targets in the complex low-altitude environment poses significant security challenges, including failures in continuous wide-area sensing and ambiguous target intent, which…
Typically, a memory request from a processor may need to go through many intermediate interconnect routers, directory node, owner node, etc before it is finally serviced. Current multiprocessors do not give preference to any particular…
Parallel programming is emerging fast and intensive applications need more resources, so there is a huge demand for on-chip multiprocessors. Accessing L1 caches beside the cores are the fastest after registers but the size of private caches…
In future sixth-generation (6G) mobile networks, radar sensing is expected to be offered as an additional service to its original purpose of communication. Merging these two functions results in integrated sensing and communication (ISAC)…
Superconducting quantum computing has the potential to revolutionize computational capabilities. However, scaling up large quantum processors is limited by the cumbersome and heat-conductive electronic cables that connect room-temperature…
Next-generation mixed-criticality Systems-on-chip (SoCs) for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ensuring reliable and time-predictable execution of critical…
High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex and high-bandwidth closed-loop power and thermal control strategies. To efficiently satisfy real-time multi-input multi-output…
Arm Cortex-M processors are the most widely used 32-bit microcontrollers among embedded and Internet-of-Things devices. Despite the widespread usage, there has been little effort in summarizing their hardware security features,…
The emerging microservice/serverless-based cloud programming paradigm and the rising networking speeds leave the RPC stack as the predominant data center tax. Domain-specific hardware acceleration holds the potential to disentangle the…