Related papers: Front End CAMAC Controller for SLAC Control System

The SNS Project intends to integrate Conventional Facility Controls with its EPICS-based Accelerator and Target Control Systems. EPICS will therefore be used to provide distributed high-level access to all subsystems of the SNS conventional…

This paper presents an in-memory computing (IMC) architecture developed on an 8x8 array of 8T SRAM cells. This architecture enables both multi-bit parallel Multiply-Accumulate (MAC) operations and standard memory processing through…

IUCAA Digital Sampling Array Controller (IDSAC) is a generic CCD Controller which is flexible and powerful enough to control a wide variety of CCDs and CMOS detectors used for ground-based astronomy. It has a fully scalable architecture,…

Low Level RF (LLRF) control systems of linear accelerators (LINACs) are typically implemented with heterodyne based architectures, which have complex analog RF mixers for up and down conversion. The Gen 3 Radio Frequency System-on-Chip…

Future wireless systems, known as gigantic multiple-input multiple-output (MIMO), are expected to enhance performance by significantly increasing the number of antennas, e.g., a few thousands. To enable gigantic MIMO overcoming the…

Microwave linear analog computers (MiLACs) have recently emerged as a promising solution for future gigantic multiple-input multiple-output (MIMO) systems, enabling beamforming with greatly reduced hardware and computational cost. However,…

The PEP-II storage rings at SLAC each have 3492 'buckets' into which electrons and positrons can be injected into the high- and low-energy rings. Equipment to measure the currents of all the individual buckets was originally provided by the…

Functional verification is a critical bottleneck in integrated circuit development, with CPU verification being especially time-intensive and labour-consuming. Industrial practice relies on differential testing for CPU verification, yet…

This paper presents the design, implementation, and performance evaluation of LUCAS, a low-power, ultra-low jitter ASIC optimized for SiPM readout in Time-of-Flight Computed Tomography (ToF-CT) applications. Leveraging a novel preamplifier…

Integrated sensing and communication (ISAC) is a key enabler for future radio networks. This paper presents a sub-band full-duplex (SBFD) ISAC system that assigns non-overlapping OFDM subbands to sensing and communication, enabling…

Integrated sensing and communications (ISAC) allows networks to perform sensing alongside data transmission. While most ISAC studies focus on single-target, multi-user scenarios, multi-target sensing is scarcely researched. This letter…

A scalable control architecture for superconducting quantum processors is essential as the number of qubits increases and coherent multi-qubit operations span beyond the capacity of a single control module. The Quantum Instrumentation…

Privacy and security have rapidly emerged as priorities in system design. One powerful solution for providing both is privacy-preserving computation, where functions are computed directly on encrypted data and control can be provided over…

This paper addresses the power control design for a cell-free massive MIMO (CF-mMIMO) system that performs integrated sensing and communications (ISAC). Specifically, the case where many access points are deployed to simultaneously…

An interlock system has been designed for the Fermilab Cryo-module Test Stand (CMTS), a test bed for the cryomodules to be used in the upcoming Linac Coherent Light Source 2 (LCLS-II) project at SLAC. The interlock system features 8…

Challenges at the quantum-classical interface are examined with the goal of architecting a scaled-up quantum computer comprising many thousands of qubits in the solid-state. Separating the distinct sub-systems of the interface that perform…

Traditional single-modality sensing faces limitations in accuracy and capability, and its decoupled implementation with communication systems increases latency in bandwidth-constrained environments. Additionally, single-task-oriented…

A modular and scalable converter for medium voltage (MV) AC to low voltage (LV) DC power conversion is proposed; single-phase-modules (SPMs), each consisting of an active-front-end (AFE) stage and an isolated DC-DC stage, are connected in…

The control system of the 1.5 MeV FEL injector is built on the base of ported EPICS. It uses low-cost hardware: personal computers with the processor Intel x86 and CAMAC equipment produced by our institute. At present time, the distributed…

Integrated sensing and communication (ISAC), as a technology enabled seamless connection between communication and sensing, is regarded a core enabling technology for these applications. However, the accuracy of single-node sensing in ISAC…