Related papers: Optimization of Lattice QCD codes for the AMD Opte…
To address growth challenges facing large Data Centers and supercomputing clusters a new construction is presented for scalable, high throughput, low latency networks. The resulting networks require 1.5-5 times fewer switches, 2-6 times…
Encoding logical quantum information in harmonic oscillator modes is a promising and hardware-efficient approach to the realization of a quantum computer. In this work, we propose to encode logical qubits in grid states of an ensemble of…
Motivated by the need for channel codes with low-complexity soft-decision decoding algorithms, we consider the recursive Plotkin concatenation of optimal low-rate and high-rate codes based on simplex codes and their duals. These component…
Linear complementary dual (LCD) codes, which is a class of linear codes introduced by Massey, have been extensively studied in literature recently. It has been shown that LCD codes can help to improve the security of the information…
We demonstrate that lattice QCD calculations can be made $10^3$--$10^6$ times faster by using very coarse lattices. To obtain accurate results, we replace the standard lattice actions by perturbatively-improved actions with tadpole-improved…
In this paper, we propose two novel modulation concepts based on a simple maximum distance separable (MDS) code { and show that these concepts can achieve better error performance than index modulation (IM) and related schemes.} In the…
We propose a novel decoding algorithm for staircase codes which reduces the effect of undetected component code miscorrections. The algorithm significantly improves performance, while retaining a low-complexity implementation suitable for…
Modern microarchitectures are some of the world's most complex man-made systems. As a consequence, it is increasingly difficult to predict, explain, let alone optimize the performance of software running on such microarchitectures. As a…
In this paper, a novel modulation scheme called set partition modulation (SPM) is proposed. In this scheme, set partitioning and ordered subsets in the set partitions are used to form codewords. We define different SPM variants and depict a…
Programmable Logic Devices (PLDs) continue to grow in size and currently contain several millions of gates. At the same time, research effort is going into higher-level hardware synthesis methodologies for reconfigurable computing that can…
Encoding logical qubits with surface codes and performing multi-qubit logical operations with lattice surgery is one of the most promising approaches to demonstrate fault-tolerant quantum computing. Thus, a method to efficiently schedule a…
In this paper, we introduce further our recently designed family of L2 orthogonal Space-Time codes for CPM. With their advantage of maintaining both the constant envelope properties of CPM, the diversity of Space-Time codes and moreover…
We propose a new decentralized coded caching scheme for a two-phase caching network, where the data placed in user caches in the prefetching phase are random portions of a maximal distance separable (MDS) coded version of the original…
We investigate implementation of lattice Quantum Chromodynamics (QCD) code on the Intel Xeon Phi Knights Landing (KNL). The most time consuming part of the numerical simulations of lattice QCD is a solver of linear equation for a large…
Recently Arm introduced a new instruction set called Scalable Vector Extension (SVE), which supports vector lengths up to 2048 bits. While SVE hardware will not be generally available until about 2021, we believe that future SVE-based…
This paper presents the interesting observation that by performing fewer of the optimizations available in a standard compiler optimization level such as -O2, while preserving their original ordering, significant savings can be achieved in…
Hardware accelerators are key to the efficiency and performance of system-on-chip (SoC) architectures. With high-level synthesis (HLS), designers can easily obtain several performance-cost trade-off implementations for each component of a…
Programming a quantum device describes the usage of quantum logic gates, agnostic of hardware specifics, to perform a sequence of operations with (typically) a computing or sensing task in mind. Such programs have been executed on digital…
Processor manufacturers build increasingly specialized processors to mitigate the effects of the power wall to deliver improved performance. Currently, database engines are manually optimized for each processor: A costly and error prone…
Neural compression has brought tremendous progress in designing lossy compressors with good rate-distortion (RD) performance at low complexity. Thus far, neural compression design involves transforming the source to a latent vector, which…