Related papers: Novel Reversible Multiplier Architecture Using Rev…
A multiplier, as a key component in many different applications, is a time-consuming, energy-intensive computation block. Approximate computing is a practical design paradigm that attempts to improve hardware efficacy while keeping…
Superconducting quantum processors have largely converged on transmon-based architectures, while alternative qubit modalities with intrinsic error protection have lacked a demonstrated path to scalable system integration. In particular,…
In recent years, machine learning techniques based on neural networks for mobile computing become increasingly popular. Classical multi-layer neural networks require matrix multiplications at each stage. Multiplication operation is not an…
Field Programmable Gate Arrays(FPGA) exceed the computing power of software based implementations by breaking the paradigm of sequential execution and accomplishing more per clock cycle by enabling hardware level parallelization at an…
Implementing quantum algorithms on realistic hardware requires translating high-level global operations into sequences of native elementary gates, a process known as quantum compiling. Physical limitations, such as constraints in…
An $(n+1)$-bit Toffoli gate is mainly utilized to construct other quantum gates and operators, such as Fredkin gates, arithmetical adders, and logical comparators, where $n \geq 2$. Several researchers introduced different methods to…
In literature, NAND and NOR are two logic gates that display functional completeness, hence regarded as Universal gates. So, the present effort is focused on exploring a library of universal gates in binary that are still unexplored in…
This article presents a research work on the design and synthesis of sequential circuits and flip-flops that are available in digital arena; and describes a new synthesis design of reversible counter that is optimized in terms of quantum…
In database design, Composite Keys are used to uniquely identify records and prevent data duplication. However, they require more memory and storage space than single keys, and can make queries more CPU-intensive. Surrogate Keys are an…
Reconfiguration has been used for both defect- and fault-tolerant nanoscale architectures with regular structure. Recent advances in self-assembled nanowires have opened doors to a new class of electronic devices with irregular structure.…
Most of the work on implementing arithmetic on a quantum computer has borrowed from results in classical reversible computing (e.g. [VBE95], [BBF02], [DKR04]). These quantum networks are inherently classical, as they can be implemented with…
We present efficient and scalable parallel algorithms for performing mathematical operations for low-rank tensors represented in the tensor train (TT) format. We consider algorithms for addition, elementwise multiplication, computing norms…
We consider the problem of constructing fast and small parallel prefix adders for non-uniform input arrival times. This problem arises whenever the adder is embedded into a more complex circuit, e. g. a multiplier. Most previous results are…
In this paper, we propose an efficient quantum carry-lookahead adder based on the higher radix structure. For the addition of two $n$-bit numbers, our adder uses $O(n)-O(\frac{n}{r})$ qubits and $O(n)+O(\frac{n}{r})$ T gates to get the…
The paper presents a systematic study and implementation of a reconfigurable combinatorial multi-operand adder for use in Deep Learning systems. The size of carry changes with the number of operands and hence a reliable algorithm to…
In this paper, reversible circuits consisting of NOT, CNOT and 2-CNOT gates are studied. Several asymptotically optimal by the order of magnitude synthesis methods are described. Some circuit's complexity reduction approaches are…
Transversal gates are the ideal gates in a fault-tolerant scenario; relatively easy to implement, and minimally error propagating. Their availability will maximise fault tolerant thresholds, enabling universal quantum computation in a wider…
Embedded Field-Programmable Gate Arrays (eFPGAs) allow for the design of hardware accelerators of edge Machine Learning (ML) applications at a lower power budget compared with traditional FPGA platforms. However, the limited eFPGA logic and…
This paper proposes a special-purpose system to achieve high-accuracy and high-efficiency machine learning (ML) molecular dynamics (MD) calculations. The system consists of field programmable gate array (FPGA) and application specific…
The data transfer between a processor and memory has become a design bottleneck in data-intensive applications. Processing-In-Memory (PIM) is a practical approach to overcome the memory wall bottleneck. The 4:2 compressor is suitable for…