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This article presents an evaluation of the computational performance and energy efficiency of the Cronos cluster, composed of Raspberry Pi4 and 3b microcomputers designed for educational purposes. Experimental tests were performed using the…

Hardware Architecture · Computer Science 2025-12-09 Martha Semken , Mariano Vargas , Ignacio Tula , Giuliana Zorzoli , Andrés Rojas Paredes

Most Wearable Ultrasound (WUS) devices lack the computational power to process signals at the edge, instead relying on remote offload, which introduces latency, high power consumption, and privacy concerns. We present Maestro, a RISC-V SoC…

One of the biggest concerns in IoT is privacy and security. Encryption and authentication need big power budgets, which battery-operated IoT end-nodes do not have. Hardware accelerators designed for specific cryptographic operations provide…

Hardware Architecture · Computer Science 2020-10-01 Ömer Faruk Irmak , Arda Yurdakul

The paradigm shift towards multi-core and heterogeneous computing, driven by the fundamental power and thermal limits of single-core processors, has established energy efficiency as a first-class design constraint in high-performance…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-07-30 Mufakir Qamar Ansari , Mudabir Qamar Ansari

Although originally developed primarily for artificial intelligence workloads, RISC-V-based accelerators are also emerging as attractive platforms for high-performance scientific computing. In this work, we present our approach to…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-09-24 Jenny Lynn Almerol , Elisabetta Boella , Mario Spera , Daniele Gregori

We use a graphics processing unit (GPU) for fast computations of Monte Carlo integrations. Two widely used Monte Carlo integration programs, VEGAS and BASES, are parallelized on GPU. By using $W^{+}$ plus multi-gluon production processes at…

Computational Physics · Physics 2011-03-03 J. Kanzaki

Modern GPUs incorporate specialized matrix units such as Tensor Cores to accelerate GEMM operations, which are central to deep learning workloads. However, existing matrix unit designs are tightly coupled to the SIMT core, restricting…

Hardware Architecture · Computer Science 2025-03-04 Hansung Kim , Ruohan Richard Yan , Joshua You , Tieliang Vamber Yang , Yakun Sophia Shao

A chiplet is an integrated circuit that encompasses a well-defined subset of an overall system's functionality. In contrast to traditional monolithic system-on-chips (SoCs), chiplet-based architecture can reduce costs and increase…

Hardware Architecture · Computer Science 2023-12-12 Shixin Chen , Shanyi Li , Zhen Zhuang , Su Zheng , Zheng Liang , Tsung-Yi Ho , Bei Yu , Alberto L. Sangiovanni-Vincentelli

We have developed a Python package ZMCintegral for multi-dimensional Monte Carlo integration on multiple Graphics Processing Units(GPUs). The package employs a stratified sampling and heuristic tree search algorithm. We have built three…

Computational Physics · Physics 2022-09-19 Hong-Zhong Wu , Jun-Jie Zhang , Long-Gang Pang , Qun Wang

Homomorphic encryption (HE) allows direct computations on encrypted data. Despite numerous research efforts, the practicality of HE schemes remains to be demonstrated. In this regard, the enormous size of ciphertexts involved in HE…

Cryptography and Security · Computer Science 2020-10-27 Dayane Reis , Jonathan Takeshita , Taeho Jung , Michael Niemier , Xiaobo Sharon Hu

We explore how the big-three computing paradigms -- symmetric multi-processor (SMC), graphical processing units (GPUs), and cluster computing -- can together be brought to bare on large-data Gaussian processes (GP) regression problems via a…

Computation · Statistics 2014-06-05 Robert B. Gramacy , Jarad Niemi , Robin M. Weiss

Sparse matrix-vector multiplication (SpMV) is a fundamental building block for numerous applications. In this paper, we propose CSR5 (Compressed Sparse Row 5), a new storage format, which offers high-throughput SpMV on various platforms…

Mathematical Software · Computer Science 2015-04-13 Weifeng Liu , Brian Vinter

The RISC-V "V" extension introduces vector processing to the RISC-V architecture. Unlike most SIMD extensions, it supports long vectors which can result in significant improvement of multiple applications. In this paper, we present our…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-11-10 Sonia Rani Gupta , Nikela Papadopoulou , Miquel Pericàs

The using of GPU for Monte Carlo particle transport is lacking of fair comparisons. This work performs simulations on both CPU and GPU in the same package under the same manufacturing process of low power mobile devices. The experiment with…

Distributed, Parallel, and Cluster Computing · Computer Science 2022-08-15 Changyuan Liu

Resource-limited robots face significant challenges in executing computationally intensive tasks, such as locomotion and manipulation, particularly for real-time optimal control algorithms like Model Predictive Control (MPC). This paper…

The emergence of chiplet-based heterogeneous integration is transforming the semiconductor, AI, and high-performance computing industries by enabling modular designs and improved scalability. However, assembling chiplets from multiple…

Cryptography and Security · Computer Science 2025-07-08 Ishraq Tashdid , Tasnuva Farheen , Sazadur Rahman

The emerging trend of deploying complex algorithms, such as Deep Neural Networks (DNNs), increasingly poses strict memory and energy efficiency requirements on Internet-of-Things (IoT) end-nodes. Mixed-precision quantization has been…

Spectroscopic and photometric data for likely member stars of five Galactic globular clusters (M3, M53, M71, M92, and NGC 5053) and three open clusters (M35, NGC 2158, and NGC 6791) are processed by the current version of the SEGUE Stellar…

Neural Networks (NNs) have been widely adopted due to their outstanding efficacy and adaptability across computer vision and deep learning applications. The optimization of NNs is necessary to enable their deployment on energy constrained…

Hardware Architecture · Computer Science 2026-05-12 Pragun Jaswal , L. Hemanth Krishna , B. Srinivasu

The ever-increasing computational and storage requirements of modern applications and the slowdown of technology scaling pose major challenges to designing and implementing efficient computer architectures. To mitigate the bottlenecks of…

Hardware Architecture · Computer Science 2025-01-10 Matteo Perotti , Samuel Riedel , Matheus Cavalcante , Luca Benini