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Related papers: HyDRA: Deadline and Reuse-Aware Cacheability for H…

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Cause-effect chains, as a widely used modeling method in real-time embedded systems, are extensively applied in various safety-critical domains. End-to-end latency, as a key real-time attribute of cause-effect chains, is crucial in many…

Systems and Control · Electrical Eng. & Systems 2026-01-29 Yixuan Zhu , Yinkang Gao , Bo Zhang , Xiaohang Gong , Binze Jiang , Lei Gong , Wenqi Lou , Teng Wang , Chao Wang , Xi Li , Xuehai Zhou

The rapid growth of multi-core systems highlights the need for efficient Network-on-Chip (NoC) design to ensure seamless communication. Cache coherence, essential for data consistency, substantially reduces task computation time by enabling…

Hardware Architecture · Computer Science 2025-06-04 Guochu Xiong , Xiangzhong Luo , Weichen Liu

Flexibility at hardware level is the main driving force behind adaptive systems whose aim is to realise microarhitecture deconfiguration 'online'. This feature allows the software/hardware stack to tolerate drastic changes of the workload…

Hardware Architecture · Computer Science 2016-12-28 Ana Lava , Mahdi Jelodari Mamaghani , Siamak Mohammadi , Steve Furber

The technologies of heterogeneous multi-core architectures, co-location, and virtualization can be used to reduce server power consumption and improve system utilization, which are three important technologies for data centers. This article…

Operating Systems · Computer Science 2023-10-24 Yecheng Yang , Pu Pang , Jiawen Wang , Quan Chen , Minyi Guo

Although benefits from caching in US HEP are well-known, current caching strategies are not adaptive i.e they do not adapt to changing cache access patterns. Newer developments such as the High-Luminosity - Large Hadron Collider (HL-LHC),…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-04-24 Venkat Sai Suman Lamba Karanam , Sarat Sasank Barla , Byrav Ramamurthy , Derek Weitzel

Domain-specific systems-on-chip, a class of heterogeneous many-core systems, are recognized as a key approach to narrow down the performance and energy-efficiency gap between custom hardware accelerators and programmable processors.…

Hardware Architecture · Computer Science 2020-08-10 Anish Krishnakumar , Samet E. Arda , A. Alper Goksoy , Sumit K. Mandal , Umit Y. Ogras , Anderson L. Sartor , Radu Marculescu

Hybrid main memory systems combine both performance and capacity advantages from heterogeneous memory technologies. With larger capacities, higher associativities, and finer granularities, hybrid memory systems currently exhibit significant…

Hardware Architecture · Computer Science 2024-08-27 Yiwei Li , Boyu Tian , Mingyu Gao

Job schedulers are a key component of scalable computing infrastructures. They orchestrate all of the work executed on the computing infrastructure and directly impact the effectiveness of the system. Recently, job workloads have…

Distributed, Parallel, and Cluster Computing · Computer Science 2018-03-06 Albert Reuther , Chansup Byun , William Arcand , David Bestor , Bill Bergeron , Matthew Hubbell , Michael Jones , Peter Michaleas , Andrew Prout , Antonio Rosa , Jeremy Kepner

Recurrent neural networks (RNNs) have shown state of the art results for speech recognition, natural language processing, image captioning and video summarizing applications. Many of these applications run on low-power platforms, so their…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-04-09 Urmish Thakker , Ganesh Dasika , Jesse Beu , Matthew Mattina

The latest trends in high-performance computing systems show an increasing demand on the use of a large scale multicore systems in a efficient way, so that high compute-intensive applications can be executed reasonably well. However, the…

Distributed, Parallel, and Cluster Computing · Computer Science 2013-02-25 Juliana M. N. Silva , Cristina Boeres , Lúcia M. A. Drummond , Artur A. Pessoa

Collaborative Edge Computing (CEC) is a new edge computing paradigm that enables neighboring edge servers to share computational resources with each other. Although CEC can enhance the utilization of computational resources, it still…

Networking and Internet Architecture · Computer Science 2025-02-18 Xingqiu He , Chaoqun You , Tony Q. S. Quek

Multi-core architectures feature an intricate hierarchy of cache memories, with multiple levels and sizes. To adequately decompose an application according to the traits of a particular memory hierarchy is a cumbersome task that may be…

Distributed, Parallel, and Cluster Computing · Computer Science 2015-11-20 Hervé Paulino , Nuno Delgado

Many HPC applications suffer from a bottleneck in the shared caches, instruction execution units, I/O or memory bandwidth, even though the remaining resources may be underutilized. It is hard for developers and runtime systems to ensure…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-03-17 Felippe V. Zacarias , Vinicius Petrucci , Rajiv Nishtala , Paul Carpenter , Daniel Mossé

Creating and destroying threads on modern Linux systems incurs high latency, absent concurrency, and fails to scale as we increase concurrency. To address this concern we introduce a process-local cache of idle threads. Specifically,…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-05-18 Dave Dice , Alex Kogan

In large-scale distributed computing clusters, such as Amazon EC2, there are several types of "system noise" that can result in major degradation of performance: bottlenecks due to limited communication bandwidth, latency due to straggler…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-06-21 Amirhossein Reisizadeh , Saurav Prakash , Ramtin Pedarsani , Amir Salman Avestimehr

Resource provisioning plays a pivotal role in determining the right amount of infrastructure resource to run applications and target the global decarbonization goal. A significant portion of production clusters is now dedicated to…

Distributed, Parallel, and Cluster Computing · Computer Science 2022-08-29 Clement Mommessin , Renyu Yang , Natalia V. Shakhlevich , Xiaoyang Sun , Satish Kumar , Junqing Xiao , Jie Xu

In modern server CPUs, the Last-Level Cache (LLC) serves not only as a victim cache for higher-level private caches but also as a buffer for low-latency DMA transfers between CPU cores and I/O devices through Direct Cache Access (DCA).…

Hardware Architecture · Computer Science 2025-06-16 Haneul Park , Jiaqi Lou , Sangjin Lee , Yifan Yuan , Kyoung Soo Park , Yongseok Son , Ipoom Jeong , Nam Sung Kim

With the advent of 5G networks and the rise of the Internet of Things (IoT), Content Delivery Networks (CDNs) are increasingly extending into the network edge. This shift introduces unique challenges, particularly due to the limited cache…

Networking and Internet Architecture · Computer Science 2024-04-05 Hoda Torabi , Hamzeh Khazaei , Marin Litoiu

In-situ LLM inference on end-user devices has gained significant interest due to its privacy benefits and reduced dependency on external infrastructure. However, as the decoding process is memory-bandwidth-bound, the diverse processing…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-06-11 Jinhui Wei , Ye Huang , Yuhui Zhou , Jiazhi Jiang , Jiangsu Du , Yutong Lu

This paper addresses emerging system-level challenges in heterogeneous retrieval-augmented generation (RAG) serving, where complex multi-stage workflows and diverse request patterns complicate efficient execution. We present HedraRAG, a…

Databases · Computer Science 2025-07-15 Zhengding Hu , Vibha Murthy , Zaifeng Pan , Wanlu Li , Xiaoyi Fang , Yufei Ding , Yuke Wang
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