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Transformers and LLMs have seen rapid adoption in all domains. Their sizes have exploded to hundreds of billions of parameters and keep increasing. Under these circumstances, the training of transformers is slow and often takes in the order…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-06-18 Avinash Maurya , Jie Ye , M. Mustafa Rafique , Franck Cappello , Bogdan Nicolae

Advances in hybrid bonding and packaging have driven growing interest in 3D DRAM-stacked accelerators with higher memory bandwidth and capacity. As LLMs scale to hundreds of billions or trillions of parameters, distributed inference across…

Autoregressive decoding with generative Large Language Models (LLMs) on accelerators (GPUs/TPUs) is often memory-bound where most of the time is spent on transferring model parameters from high bandwidth memory (HBM) to cache. On the other…

Machine Learning · Computer Science 2024-02-15 Yashas Samaga B L , Varun Yerram , Chong You , Srinadh Bhojanapalli , Sanjiv Kumar , Prateek Jain , Praneeth Netrapalli

In-DRAM Processing-In-Memory (DRAM-PIM) has emerged as a promising approach to accelerate memory-intensive workloads by mitigating data transfer overhead between DRAM and the host processor. Bit-serial DRAM-PIM architectures, further…

Hardware Architecture · Computer Science 2025-12-11 Siyuan Ma , Jiajun Hu , Jeeho Ryoo , Aman Arora , Lizy Kurian John

The rapid growth of LLMs demands high-throughput, memory-capacity-intensive inference on resource-constrained edge devices, where single-batch decoding remains fundamentally memory-bound. Existing out-of-core GPU-based and SSD-like…

Hardware Architecture · Computer Science 2026-04-29 Mingbo Hao , Changwei Yan , Haoyu Cui , Zhihao Yan , Yizhi Ding , Zhangrui Qian , Weiwei Shan

Large Language Model (LLM) inference is rapidly becoming a core datacenter service, yet current serving stacks keep the host CPU on the critical path for orchestration and token-level control. This makes LLM performance sensitive to CPU…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-04-10 Mohammad Siavashi , Mariano Scazzariello , Gerald Q. Maguire , Dejan Kostić , Marco Chiesa

LLMs now form the backbone of AI agents across a diverse range of applications, including tool use, command-line interfaces, and web or computer interaction. These agentic LLM inference tasks are fundamentally different from chatbot-focused…

Personalized recommendation is a ubiquitous application on the internet, with many industries and hyperscalers extensively leveraging Deep Learning Recommendation Models (DLRMs) for their personalization needs (like ad serving or movie…

Hardware Architecture · Computer Science 2024-10-30 Rishabh Jain , Vivek M. Bhasi , Adwait Jog , Anand Sivasubramaniam , Mahmut T. Kandemir , Chita R. Das

We propose overcoming the memory capacity limitation of GPUs with high-capacity Storage-Class Memory (SCM) and DRAM cache. By significantly increasing the memory capacity with SCM, the GPU can capture a larger fraction of the memory…

Hardware Architecture · Computer Science 2024-03-15 Jeongmin Hong , Sungjun Cho , Geonwoo Park , Wonhyuk Yang , Young-Ho Gong , Gwangsun Kim

Large-scale deep neural networks (DNNs), such as large language models (LLMs), have revolutionized the artificial intelligence (AI) field and become increasingly popular. However, training or fine-tuning such models requires substantial…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-01-17 Cong Guo , Rui Zhang , Jiale Xu , Jingwen Leng , Zihan Liu , Ziyu Huang , Minyi Guo , Hao Wu , Shouren Zhao , Junping Zhao , Ke Zhang

When executing a deep neural network (DNN), its model parameters are loaded into GPU memory before execution, incurring a significant GPU memory burden. There are studies that reduce GPU memory usage by exploiting CPU memory as a swap…

Machine Learning · Computer Science 2022-10-11 Mingoo Ji , Saehanseul Yi , Changjin Koo , Sol Ahn , Dongjoo Seo , Nikil Dutt , Jong-Chan Kim

With the rapid adoption of Large Language Models (LLMs), LLM-adapters have become increasingly common, providing lightweight specialization of large-scale models. Serving hundreds or thousands of these adapters on a single GPU allows…

Over the past two decades, the storage capacity and access bandwidth of main memory have improved tremendously, by 128x and 20x, respectively. These improvements are mainly due to the continuous technology scaling of DRAM (dynamic…

Hardware Architecture · Computer Science 2017-12-25 Kevin K. Chang

In modern systems, DRAM-based main memory is significantly slower than the processor. Consequently, processors spend a long time waiting to access data from main memory, making the long main memory access latency one of the most critical…

Hardware Architecture · Computer Science 2016-11-01 Donghyuk Lee

Modern large language models (LLMs) increasingly depends on efficient long-context processing and generation mechanisms, including sparse attention, retrieval-augmented generation (RAG), and compressed contextual memory, to support complex…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-05-12 Zifan He , Rui Ma , Yizhou Sun , Jason Cong

The increasing deployment of Large Language Model (LLM) inference on edge AI systems demands efficient execution under tight memory budgets. A key challenge arises from Key-Value (KV) caches, which often exceed available device memory.…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-04-30 Bodon Jeong , Hongsu Byun , Youngjae Kim , Weikuan Yu , Kyungkeun Lee , Jihoon Yang , Sungyong Park

Graphics Processing Units (GPUs) have traditionally relied on the host CPU to initiate access to the data storage. This approach is well-suited for GPU applications with known data access patterns that enable partitioning of their dataset…

The widespread of Large Language Models (LLMs) marks a significant milestone in generative AI. Nevertheless, the increasing context length and batch size in offline LLM inference escalate the memory requirement of the key-value (KV) cache,…

Hardware Architecture · Computer Science 2024-09-10 Xiurui Pan , Endian Li , Qiao Li , Shengwen Liang , Yizhou Shan , Ke Zhou , Yingwei Luo , Xiaolin Wang , Jie Zhang

Indirect memory accesses frequently appear in applications where memory bandwidth is a critical bottleneck. Prior indirect memory access proposals, such as indirect prefetchers, runahead execution, fetchers, and decoupled access/execute…

Conventional wisdom holds that an efficient interface between an OS running on a CPU and a high-bandwidth I/O device should use Direct Memory Access (DMA) to offload data transfer, descriptor rings for buffering and queuing, and interrupts…

Hardware Architecture · Computer Science 2025-04-25 Anastasiia Ruzhanskaia , Pengcheng Xu , David Cock , Timothy Roscoe