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Modern distributed systems demand low-latency, fault-tolerant event processing that exceeds traditional messaging architecture limits. While frameworks including Apache Kafka, RabbitMQ, Apache Pulsar, NATS JetStream, and serverless event…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-10-24 Jahidul Arafat , Fariha Tasmin , Sanjaya Poudel

The growing concern for energy efficiency in the Information and Communication Technology (ICT) sector has prompted the exploration of resource management techniques. While hardware architectures, such as single-ISA asymmetric multicore…

Programming Languages · Computer Science 2024-03-05 Marina Shimchenko , Erik Österlund , Tobias Wrigstad

Message brokers see widespread adoption in modern IT landscapes, with Apache Kafka being one of the most employed platforms. These systems feature well-defined APIs for use and configuration and present flexible solutions for various data…

Performance · Computer Science 2021-03-04 Guenter Hesse , Christoph Matthies , Matthias Uflacker

Performance evaluation of the routing node in terms of latency is the characteristics of an efficient design of Buffer in input module. It is intended to study and quantify the behavior of the single packet array design in relation to the…

Hardware Architecture · Computer Science 2013-02-19 Nilesh A. Mohota , Sanjay L. Badjate

One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at very high speeds and to the fact that in order to support…

Hardware Architecture · Computer Science 2011-11-09 I. Papaefstathiou , T. Orphanoudakis , G. Kornaros , C. Kachris , I. Mavroidis , A. Nikologiannis

This work elaborates on a High performance computing (HPC) architecture based on Simple Linux Utility for Resource Management (SLURM) [1] for deploying heterogeneous Large Language Models (LLMs) into a scalable inference engine. Dynamic…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-08-26 Anderson de Lima Luiz , Shubham Vijay Kurlekar , Munir Georges

The adoption of very low latency persistent memory modules (PMMs) upends the long-established model of disaggregated file system access. Instead, by colocating computation and PMM storage, we can provide applications much higher I/O…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-06-03 Thomas E. Anderson , Marco Canini , Jongyul Kim , Dejan Kostić , Youngjin Kwon , Simon Peter , Waleed Reda , Henry N. Schuh , Emmett Witchel

Following the scale-up of new radio (NR) complexity in 5G and beyond, the physical layer's computing load on base stations is increasing under a strictly constrained latency and power budget; base stations must process > 20-Gb/s uplink…

Signal Processing · Electrical Eng. & Systems 2025-08-11 Marco Bertuletti , Yichao Zhang , Alessandro Vanelli-Coralli , Luca Benini

Load balancing across parallel servers is an important class of congestion control problems that arises in service systems. An effective load balancer relies heavily on accurate, real-time congestion information to make routing decisions.…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-05-24 Gal Mendelson , Xu Kuang

Token generation speed is critical to power the next wave of AI inference applications. GPUs significantly underperform during token generation due to synchronization overheads at kernel boundaries, utilizing only 21% of their peak memory…

Data are gathered from the Parkes pulsar data archive of twelve young radio pulsars, with the intervals of data for each pulsar ranged between 2.8 years and 6.8 years. 31 glitches are identified by using phase connection from "pulsar…

High Energy Astrophysical Phenomena · Physics 2018-06-15 S. Q. Zhou , J. P. Yuan , J. Zhang , M. Q. Liu , Z. W. Feng. S. J. Dang , X. D. Zhu

Over the years, processor throughput has steadily increased. However, the memory throughput has not increased at the same rate, which has led to the memory wall problem in turn increasing the gap between effective and theoretical peak…

Hardware Architecture · Computer Science 2022-01-31 Furkan Eris , Marcia S. Louis , Kubra Eris , Jose L. Abellan , Ajay Joshi

Approaching ideal wire latency using a network-on-chip (NoC) is an important practical problem for many-core systems, particularly hundreds-cores. Although other researchers have focused on optimizing large meshes, bypassing or speculating…

Hardware Architecture · Computer Science 2016-07-28 Giorgos Passas

A noise-tolerant data communications fabric has been developed to meet the real-time data acquisition and control requirements of fast feedback loops, machine protection systems, pulse-to-pulse sequencing, and machine-experiment…

Instrumentation and Detectors · Physics 2007-05-23 E. J. Siskind

Memory-disk synchronization is a critical technology for ensuring data correctness, integrity, and security, especially in systems that handle sensitive information like financial transactions and medical records. We propose SYNC+SYNC, a…

Cryptography and Security · Computer Science 2025-01-17 Congcong Chen , Jinhua Cui , Gang Qu , Jiliang Zhang

Apache Kafka addresses the general problem of delivering extreme high volume event data to diverse consumers via a publish-subscribe messaging system. It uses partitions to scale a topic across many brokers for producers to write data in…

Networking and Internet Architecture · Computer Science 2024-10-28 Theofanis P. Raptis , Andrea Passarella

The performance of AI accelerators is increasingly limited by data movement, memory access, and orchestration overheads rather than raw compute capability. This paper presents MAVeC, a messaging-based adaptive vector computing accelerator…

Hardware Architecture · Computer Science 2026-02-05 Md. Rownak Hossain Chowdhury , Mostafizur Rahman

An ultra-high throughput low-density parity check (LDPC) decoder with an unrolled full-parallel architecture is proposed, which achieves the highest decoding throughput compared to previously reported LDPC decoders in the literature. The…

We present MoonGen, a flexible high-speed packet generator. It can saturate 10 GbE links with minimum sized packets using only a single CPU core by running on top of the packet processing framework DPDK. Linear multi-core scaling allows for…

Networking and Internet Architecture · Computer Science 2016-04-04 Paul Emmerich , Sebastian Gallenmüller , Daniel Raumer , Florian Wohlfart , Georg Carle

Message aggregation is often used with a goal to reduce communication cost in HPC applications. The difference in the order of overhead of sending a message and cost of per byte transferred motivates the need for message aggregation, for…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-11-07 Kavitha Chandrasekar , Laxmikant Kale
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