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The exponential emergence of Field Programmable Gate Array (FPGA) has accelerated the research of hardware implementation of Deep Neural Network (DNN). Among all DNN processors, domain specific architectures, such as, Google's Tensor…

Hardware Architecture · Computer Science 2022-02-15 Rourab Paul , Sreetama Sarkar , Suman Sau , Koushik Chakraborty , Sanghamitra Roy , Amlan Chakrabarti

Fine-grained runtime power management techniques could be promising solutions for power reduction. Therefore, it is essential to establish accurate power monitoring schemes to obtain dynamic power variation in a short period (i.e., tens or…

Hardware Architecture · Computer Science 2020-09-04 Zhe Lin , Wei Zhang , Sharad Sinha

The continuous growth of big data applications with high computational and scalability demands has resulted in increasing popularity of cloud computing. Optimizing the performance and power consumption of cloud resources is therefore…

Hardware Architecture · Computer Science 2019-10-30 Sahand Salamat , Behnam Khaleghi , Mohsen Imani , Tajana Rosing

Data center loads have expanded significantly in recent years. Compared to traditional loads, data centers are highly sensitive to voltage deviations and thus their protection mechanisms trip more proactively during voltage fluctuations.…

Systems and Control · Electrical Eng. & Systems 2025-10-07 Yiheng Xie , Wenqi Cui , Adam Wierman

Field programmable gate arrays (FPGAs) provide designers with the ability to quickly create hardware circuits. Increases in FPGA configurable logic capacity and decreasing FPGA costs have enabled designers to more readily incorporate FPGAs…

Hardware Architecture · Computer Science 2011-11-09 Roman Lysecky , Frank Vahid

The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to lower the DRAM supply voltage conservatively, which reduces some of the DRAM…

Cutting edge FPGAs are not energy efficient as conventionally presumed to be, and therefore, aggressive power-saving techniques have become imperative. The clock rate of an FPGA-mapped design is set based on worst-case conditions to ensure…

Hardware Architecture · Computer Science 2019-11-19 Behnam Khaleghi , Sahand Salamat , Mohsen Imani , Tajana Rosing

The slowdown of Moore's law and the power wall necessitates a shift towards finely tunable precision (a.k.a. transprecision) computing to reduce energy footprint. Hence, we need circuits capable of performing floating-point operations on a…

Hardware Architecture · Computer Science 2020-07-06 Stefan Mach , Fabian Schuiki , Florian Zaruba , Luca Benini

A variety of computing platform like Field Programmable Gate Array (FPGA), Graphics Processing Unit (GPU) and multicore Central Processing Unit (CPU) in data centers are suitable for acceleration of data-intensive workloads. Especially,…

Hardware Architecture · Computer Science 2023-11-21 Rourab Paul , Marco Danelutto

The current over-provisioned heterogeneous multi-cores require effective run-time optimization strategies, and the run-time power monitoring subsystem is paramount for their success. Several state-of-the-art methodologies address the design…

Hardware Architecture · Computer Science 2025-01-30 Andrea Galimberti , Michele Piccoli , Davide Zoni

With FPGAs now being deployed in the cloud and at the edge, there is a need for scalable design methods which can incorporate the heterogeneity present in the hardware and software components of FPGA systems. Moreover, these FPGA systems…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-01-29 Anuj Vaishnav , Khoa Dang Pham , Joseph Powell , Dirk Koch

Energy harvesting is an attractive way to power future IoT devices since it can eliminate the need for battery or power cables. However, harvested energy is intrinsically unstable. While FPGAs have been widely adopted in various embedded…

Hardware Architecture · Computer Science 2020-02-07 Xinyi Zhang , Clay Patterson , Yongpan Liu , Chengmo Yang , Chun Jason Xue , Jingtong Hu

Recent efforts in open-source GPU research are opening new avenues in a domain that has long been tightly coupled with a few commercial vendors. Emerging open GPU architectures define SIMT functionality through their own ISAs, but executing…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-11-19 Shinnung Jeong , Chihyo Ahn , Huanzhi Pu , Jisheng Zhao , Hyesoon Kim , Blaise Tine

Embedded Field-Programmable Gate Arrays (eFPGAs) allow for the design of hardware accelerators of edge Machine Learning (ML) applications at a lower power budget compared with traditional FPGA platforms. However, the limited eFPGA logic and…

Hardware Architecture · Computer Science 2025-02-13 Tousif Rahman , Gang Mao , Bob Pattison , Sidharth Maheshwari , Marcos Sartori , Adrian Wheeldon , Rishad Shafik , Alex Yakovlev

We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate…

This paper summarizes our work on experimental characterization and analysis of reduced-voltage operation in modern DRAM chips, which was published in SIGMETRICS 2017, and examines the work's significance and future potential. We take a…

AI acceleration has been dominated by GPUs, but the growing need for lower latency, energy efficiency, and fine-grained hardware control exposes the limits of fixed architectures. In this context, Field-Programmable Gate Arrays (FPGAs)…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-11-18 Arturo Urías Jiménez

Field Programmable Gate Arrays (FPGAs) have recently been increasingly used for highly-parallel processing of compute intensive tasks. This paper introduces an FPGA hardware platform architecture that is PC-based, allows for fast…

Hardware Architecture · Computer Science 2007-05-23 Andreas Weisensee , Darran Nathan

Even with generational improvements in DRAM technology, memory access latency still remains the major bottleneck for application accelerators, primarily due to limitations in memory interface IPs which cannot fully account for variations in…

Hardware Architecture · Computer Science 2021-08-24 Sasindu Wijeratne , Sanket Pattnaik , Zhiyu Chen , Rajgopal Kannan , Viktor Prasanna

The advent of unmanned aerial vehicles (UAVs) has improved a variety of fields by providing a versatile, cost-effective and accessible platform for implementing state-of-the-art algorithms. To accomplish a broader range of tasks, there is a…

Systems and Control · Electrical Eng. & Systems 2024-03-29 Sharif Azem , David Scheunert , Mengguang Li , Jonas Gehrunger , Kai Cui , Christian Hochberger , Heinz Koeppl
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