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Neural networks (NNs) are growing in importance and complexity. A neural network's performance (and energy efficiency) can be bound either by computation or memory resources. The processing-in-memory (PIM) paradigm, where computation is…

Hardware Architecture · Computer Science 2023-03-28 Geraldo F. Oliveira , Juan Gómez-Luna , Saugata Ghose , Amirali Boroumand , Onur Mutlu

Homomorphic encryption (HE) is a promising technology for confidential cloud computing, as it allows computations on encrypted data. However, HE is computationally expensive and often memory-bound on conventional computer architectures.…

Cryptography and Security · Computer Science 2026-05-12 Niklas Klinger , Jonas Sander , Peterson Yuhala , Pascal Felber , Thomas Eisenbarth

With the rapid growth of deep neural networks (DNNs), compute-in-memory (CIM) has emerged as a promising energy-efficient paradigm for accelerating multiply-and-accumulate (MAC) operations. Yet, current CIM architectures are largely limited…

Hardware Architecture · Computer Science 2026-04-16 Subhradip Chakraborty , Ankur Singh , Akhilesh R. Jaiswal

Computing-In-Memory (CIM) offers a potential solution to the memory wall issue and can achieve high energy efficiency by minimizing data movement, making it a promising architecture for edge AI devices. Lightweight models like MobileNet and…

Hardware Architecture · Computer Science 2025-08-21 Choongseok Song , Doo Seok Jeong

In-memory computing promises to overcome the von Neumann bottleneck in computer systems by performing computations directly within the memory. Previous research has suggested using Spin-Transfer Torque RAM (STT-RAM) for in-memory computing…

Computers and Society · Computer Science 2024-07-30 Dhruv Gajaria , Kevin Antony Gomez , Tosiron Adegbija

Conventional LLM inference architectures suffer from high energy and latency due to frequent data movement across memory hierarchies. We propose Ouroboros, a wafer-scale SRAM-based Computing-in-Memory (CIM) architecture that executes all…

Hardware Architecture · Computer Science 2026-03-04 Yiqi Liu , Yudong Pan , Mengdi Wang , Shixin Zhao , Haonan Zhu , Yinhe Han , Lei Zhang , Ying Wang

This paper summarizes the idea of Low-Cost Interlinked Subarrays (LISA), which was published in HPCA 2016, and examines the work's significance and future potential. Contemporary systems perform bulk data movement movement inefficiently, by…

Hardware Architecture · Computer Science 2018-05-09 Kevin K. Chang , Prashant J. Nair , Saugata Ghose , Donghyuk Lee , Moinuddin K. Qureshi , Onur Mutlu

The performance of today's in-memory indexes is bottlenecked by the memory latency/bandwidth wall. Processing-in-memory (PIM) is an emerging approach that potentially mitigates this bottleneck, by enabling low-latency memory access whose…

This paper presents 6T SRAM cell-based bit-parallel in-memory computing (IMC) architecture to support various computations with reconfigurable bit-precision. In the proposed technique, bit-line computation is performed with a short WL…

Hardware Architecture · Computer Science 2020-08-11 Kyeongho Lee , Jinho Jeong , Sungsoo Cheon , Woong Choi , Jongsun Park

Processing-using-DRAM has been proposed for a limited set of basic operations (i.e., logic operations, addition). However, in order to enable the full adoption of processing-using-DRAM, it is necessary to provide support for more complex…

Computing on encrypted data is a promising approach to reduce data security and privacy risks, with homomorphic encryption serving as a facilitator in achieving this goal. In this work, we accelerate homomorphic operations using the…

Cryptography and Security · Computer Science 2023-10-04 Harshita Gupta , Mayank Kabra , Juan Gómez-Luna , Konstantinos Kanellopoulos , Onur Mutlu

Bit-level sparsity in neural network models harbors immense untapped potential. Eliminating redundant calculations of randomly distributed zero-bits significantly boosts computational efficiency. Yet, traditional digital SRAM-PIM…

Hardware Architecture · Computer Science 2024-04-16 Cenlin Duan , Jianlei Yang , Yiou Wang , Yikun Wang , Yingjie Qi , Xiaolin He , Bonan Yan , Xueyan Wang , Xiaotao Jia , Weisheng Zhao

In this paper, we propose a novel memory-centric scheme based on CMOS SRAM for acceleration of data intensive applications. Our proposal aims at dynamically increasing the on-chip memory storage capacity of SRAM arrays on-demand. The…

Hardware Architecture · Computer Science 2021-09-08 Haripriya Sheshadri , Shwetha Vijayakumar , Ajey Jacob , Akhilesh Jaiswal

Computing-in-memory (CIM) is proposed to alleviate the processor-memory data transfer bottleneck in traditional Von-Neumann architectures, and spintronics-based magnetic memory has demonstrated many facilitation in implementing CIM…

Emerging Technologies · Computer Science 2020-06-03 Xueyan Wang , Jianlei Yang , Yinglin Zhao , Xiaotao Jia , Gang Qu , Weisheng Zhao

Compute-in-memory (CIM) techniques are widely employed in energy-efficient artificial intelligent (AI) processors. They alleviate power and latency bottlenecks caused by extensive data movements between compute and storage units. To extend…

Hardware Architecture · Computer Science 2025-12-15 Jianyi Yu , Tengxiao Wang , Yuxuan Wang , Xiang Fu , Fei Qiao , Ying Wang , Rui Yuan , Liyuan Liu , Cong Shi

Processing-in-memory (PIM) is a promising computing paradigm to tackle the "memory wall" challenge. However, PIM system-level benefits over traditional von Neumann architecture can be reduced when the memory array cannot fully store all the…

Hardware Architecture · Computer Science 2025-03-03 Peilin Chen , Xiaoxuan Yang

Many applications heavily use bitwise operations on large bitvectors as part of their computation. In existing systems, performing such bulk bitwise operations requires the processor to transfer a large amount of data on the memory channel,…

Hardware Architecture · Computer Science 2020-04-07 Vivek Seshadri , Onur Mutlu

Processing-in-Memory (PIM) is a promising approach to overcoming the memory-wall bottleneck. However, the PIM community has largely treated its two fundamental data layouts, Bit-Parallel (BP) and Bit-Serial (BS), as if they were…

Hardware Architecture · Computer Science 2025-10-01 Jingyao Zhang , Elaheh Sadredini

Sorting is a fundamental operation across numerous computational domains. Traditionally, this process involves transferring data from main memory to a processing unit for sorting, followed by writing the sorted data back to memory. This…

Hardware Architecture · Computer Science 2026-05-18 Narendra Singh Dhakad , Santosh Kumar Vishvakarma

Computing-in-memory (CIM) has been demonstrated across various memory technologies, ranging from memristive crossbars performing analog dot-product computations to large-scale digital bitwise operations in commodity DRAM and other proposed…

Hardware Architecture · Computer Science 2025-04-25 João Paulo Cardoso de Lima , Benjamin Franklin Morris , Asif Ali Khan , Jeronimo Castrillon , Alex K. Jones