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This paper introduces Helix, a distributed system for high-throughput, low-latency large language model (LLM) serving in heterogeneous GPU clusters. The key idea behind Helix is to formulate inference computation of LLMs over heterogeneous…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-03-07 Yixuan Mei , Yonghao Zhuang , Xupeng Miao , Juncheng Yang , Zhihao Jia , Rashmi Vinayak

Concurrent computation and communication (C3) is a pervasive paradigm in ML and other domains, making its performance optimization crucial. In this paper, we carefully characterize C3 in ML on GPUs, which are most widely deployed for ML…

Hardware Architecture · Computer Science 2025-04-28 Anirudha Agrawal , Shaizeen Aga , Suchita Pati , Mahzabeen Islam

Modern deployment of large language models (LLMs) frequently involves both inference serving and continuous retraining to stay aligned with evolving data and user feedback. Common practices separate these workloads onto distinct servers in…

Artificial Intelligence · Computer Science 2025-07-30 Yufei Li , Zexin Li , Yinglun Zhu , Cong Liu

FPGAs are increasingly prevalent in cloud deployments, serving as Smart NICs or network-attached accelerators. Despite their potential, developing distributed FPGA-accelerated applications remains cumbersome due to the lack of appropriate…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-12-20 Zhenhao He , Dario Korolija , Yu Zhu , Benjamin Ramhorst , Tristan Laan , Lucian Petrica , Michaela Blott , Gustavo Alonso

Large language model (LLM) decoding suffers from high latency due to fragmented execution across operators and heavy reliance on off-chip memory for data exchange and reduction. This execution model limits opportunities for fusion and…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-08-27 Xinhao Luo , Zihan Liu , Yangjie Zhou , Shihan Fang , Ziyu Huang , Yu Feng , Chen Zhang , Shixuan Sun , Zhenzhe Zheng , Jingwen Leng , Minyi Guo

The Compute Express Link (CXL) interconnect makes it feasible to integrate diverse types of memory into servers via its byte-addressable SerDes links. Considering the various access latency, harnessing the full potential of CXL-based…

Hardware Architecture · Computer Science 2024-09-12 Zhe Zhou , Yiqi Chen , Tao Zhang , Yang Wang , Ran Shu , Shuotao Xu , Peng Cheng , Lei Qu , Yongqiang Xiong , Jie Zhang , Guangyu Sun

Conventional heterogeneous computing systems built on PCIe interconnects suffer from inefficient fine-grained host-device interactions and complex programming models. In recent years, many proprietary and open cache-coherent interconnect…

Hardware Architecture · Computer Science 2026-01-13 Yanjing Wang , Lizhou Wu , Sunfeng Gao , Yibo Tang , Junhui Luo , Zicong Wang , Yang Ou , Dezun Dong , Nong Xiao , Mingche Lai

CXL (Compute Express Link) enables multiple hosts to share byte-addressable memory with hardware cache coherence, but no existing filesystem exploits this for lock-free multi-host coordination. We present DaxFS, a Linux filesystem for CXL…

Operating Systems · Computer Science 2026-04-03 Cong Wang , Yiwei Yang , Yusheng Zheng

Compute Express Link (CXL) serves as a rising industry standard, delivering high-speed cache-coherent links to a variety of devices, including host CPUs, computational accelerators, and memory devices. It is designed to promote system…

Hardware Architecture · Computer Science 2024-11-14 Yuda An , Shushu Yi , Bo Mao , Qiao Li , Mingzhe Zhang , Ke Zhou , Nong Xiao , Guangyu Sun , Xiaolin Wang , Yingwei Luo , Jie Zhang

Recently, large language models (LLMs) have achieved huge success in the natural language processing (NLP) field, driving a growing demand to extend their deployment from the cloud to edge devices. However, deploying LLMs on…

Hardware Architecture · Computer Science 2025-05-08 Yanbiao Liang , Huihong Shi , Haikuo Shao , Zhongfeng Wang

RAPID-LLM is a unified performance modeling framework for large language model (LLM) training and inference on GPU clusters. It couples a DeepFlow-based frontend that generates hardware-aware, operator-level Chakra execution traces from an…

Object-level management of tiered memory has been studied to address the inefficiencies in page-based systems. However, object-level management for CXL-tiered memory remains underexplored due to CXL's tight performance budget and load/store…

Operating Systems · Computer Science 2026-05-21 Sam Son , Zhihong Luo , Wen Zhang , Sylvia Ratnasamy , Scott Shenker

Serving large language models (LLMs) is expensive, especially for providers hosting many models, making cost reduction essential. The unique workload patterns of serving multiple LLMs (i.e., multi-LLM serving) create new opportunities and…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-05-14 Shan Yu , Jiarong Xing , Yifan Qiao , Mingyuan Ma , Yangmin Li , Yang Wang , Shuo Yang , Zhiqiang Xie , Shiyi Cao , Ke Bao , Ion Stoica , Harry Xu , Ying Sheng

As the memory channel count is confined by physical dimensions, memory expanders appear to be a promising approach to extending memory capacity and channels by augmenting the existing I/O interface (e.g., PCIe) with memory-semantic…

Hardware Architecture · Computer Science 2026-03-30 Younghoon Ko , Hyemin Park , Hyuk-Jae Lee , Hyokeun Lee

Machine learning models are increasingly being trained across multiple GPUs and servers. In this setting, data is transferred between GPUs using communication collectives such as AlltoAll and AllReduce, which can become a significant…

Distributed, Parallel, and Cluster Computing · Computer Science 2022-10-06 Aashaka Shah , Vijay Chidambaram , Meghan Cowan , Saeed Maleki , Madan Musuvathi , Todd Mytkowicz , Jacob Nelson , Olli Saarikivi , Rachee Singh

The Compute Express Link (CXL) technology facilitates the extension of CPU memory through byte-addressable SerDes links and cascaded switches, creating complex heterogeneous memory systems where CPU access to various endpoints differs in…

Hardware Architecture · Computer Science 2025-11-06 Yiqi Chen , Xiping Dong , Zhe Zhou , Zhao Wang , Jie Zhang , Guangyu Sun

Data Parallelism (DP), Tensor Parallelism (TP), and Pipeline Parallelism (PP) are the three strategies widely adopted to enable fast and efficient Large Language Model (LLM) training. However, these approaches rely on data-intensive…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-09-05 Lang Xu , Quentin Anthony , Qinghua Zhou , Nawras Alnaasan , Radha R. Gulhane , Aamir Shafi , Hari Subramoni , Dhabaleswar K. Panda

Distributed deep neural network training necessitates efficient GPU collective communications, which are inherently susceptible to deadlocks. GPU collective deadlocks arise easily in distributed deep learning applications when multiple…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-03-17 Lichen Pan , Juncheng Liu , Yongquan Fu , Jinhui Yuan , Rongkai Zhang , Pengze Li , Zhen Xiao

GPUs have limited memory and it is difficult to train wide and/or deep models that cause the training process to go out of memory. It is shown in this paper how an open source tool called Large Model Support (LMS) can utilize a high…

Distributed, Parallel, and Cluster Computing · Computer Science 2018-11-30 Samuel Matzek , Max Grossman , Minsik Cho , Anar Yusifov , Bryant Nelson , Amit Juneja

Distributed machine learning (DML) technology makes it possible to train large neural networks in a reasonable amount of time. Meanwhile, as the computing power grows much faster than network capacity, network communication has gradually…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-08-11 Xinchi Han , Weihao Jiang , Peirui Cao , Qinwei Yang , Yunzhuo Liu , Shuyao Qi , Shengkai Lin , Shizhen Zhao
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