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Multiplication is indispensable and is one of the core operations in many modern applications including signal processing and neural networks. Conventional right-to-left (RL) multiplier extensively contributes to the power consumption, area…

Hardware Architecture · Computer Science 2023-05-17 Muhammad Usman , Milos Ercegovac , Jeong-A Lee

Today every circuit has to face the power consumption issue for both portable device aiming at large battery life and high end circuits avoiding cooling packages and reliability issues that are too complex. It is generally accepted that…

Hardware Architecture · Computer Science 2010-07-15 C. N. Marimuthu , P. Thangaraj , Aswathy Ramesan

Neural Networks (NNs) have been widely adopted due to their outstanding efficacy and adaptability across computer vision and deep learning applications. The optimization of NNs is necessary to enable their deployment on energy constrained…

Hardware Architecture · Computer Science 2026-05-12 Pragun Jaswal , L. Hemanth Krishna , B. Srinivasu

This paper proposes an low power approximate multiplier architecture for deep neural network (DNN) applications. A 4:2 compressor, introducing only a single combination error, is designed and integrated into an 8x8 unsigned multiplier. This…

Hardware Architecture · Computer Science 2025-09-03 Pragun Jaswal , L. Hemanth Krishna , B. Srinivasu

Optical neural networks (ONN) based on micro-ring resonators (MRR) have emerged as a promising alternative to significantly accelerating the massive matrix-vector multiplication (MVM) operations in artificial intelligence (AI) applications.…

Hardware Architecture · Computer Science 2024-09-10 Bo Xu , Yuetong Fang , Shaoliang Yu , Renjing Xu

Multiplication is a fundamental operation in many applications, and multipliers are widely adopted in various circuits. However, optimizing multipliers is challenging due to the extensive design space. In this paper, we propose a multiplier…

Hardware Architecture · Computer Science 2024-12-30 Dongsheng Zuo , Jiadong Zhu , Yikang Ouyang , Yuzhe Ma

Recently, the demand of low-power deep-learning hardware for industrial applications has been increasing. Most existing artificial intelligence (AI) chips have evolved to rely on new chip technologies rather than on radically new hardware…

Machine Learning · Computer Science 2020-02-14 Byungik Ahn

Vector-Matrix Multiplication (VMM) is the fundamental and frequently required computation in inference of Neural Networks (NN). Due to the large data movement required during inference, VMM can benefit greatly from in-memory computing.…

Hardware Architecture · Computer Science 2025-10-03 Felix Zeller , John Reuben , Dietmar Fey

This brief addresses the problem of implementing very large constant multiplications by a single variable under the shift-adds architecture using a minimum number of adders/subtractors. Due to the intrinsic complexity of the problem, we…

Cryptography and Security · Computer Science 2022-05-24 Levent Aksoy , Debapriya Basu Roy , Malik Imran , Patrick Karl , Samuel Pagliarini

Large language model (LLM) decoding is a major inference bottleneck because its low arithmetic intensity makes performance highly sensitive to memory bandwidth. 3D-stacked near-memory processing (NMP) provides substantially higher local…

Hardware Architecture · Computer Science 2026-04-10 Chenyang Ai , Yixing Zhang , Haoran Wu , Yudong Pan , Lechuan Zhao , Wenhui OU

While reduction in feature size makes computation cheaper in terms of latency, area, and power consumption, performance of emerging data-intensive applications is determined by data movement. These trends have introduced the concept of…

Hardware Architecture · Computer Science 2018-03-19 Bahar Asgari , Saibal Mukhopadhyay , Sudhakar Yalamanchili

Convolutional neural networks are constructed with massive operations with different types and are highly computationally intensive. Among these operations, multiplication operation is higher in computational complexity and usually requires…

Computer Vision and Pattern Recognition · Computer Science 2025-09-18 Yulan Guo , Longguang Wang , Wendong Mao , Xiaoyu Dong , Yingqian Wang , Li Liu , Wei An

Fast combinational multipliers with large bit widths can occupy significant silicon area, which also drives up power consumption. Area can be reduced through resource sharing (i.e., folding) at the expense of lower throughput, which is…

Hardware Architecture · Computer Science 2025-09-03 Ahmad Houraniah , H. Fatih Ugurdag , C. Emre Dedeagac

The emerging mobile devices in this era of internet-of-things (IoT) require a dedicated processor to enable computationally intensive applications such as neuromorphic computing and signal processing. Vector-by-matrix multiplication (VMM)…

Signal Processing · Electrical Eng. & Systems 2020-01-08 Shubham Sahay , Mohammad Bavandpour , Mohammad Reza Mahmoodi , Dmitri Strukov

General matrix-matrix multiplication (GEMM) is a cornerstone of AI computations, making tensor processing engines (TPEs) increasingly critical in GPUs and domain-specific architectures. Existing architectures primarily optimize dataflow or…

Hardware Architecture · Computer Science 2025-03-11 Qizhe Wu , Huawen Liang , Yuchen Gui , Zhichen Zeng , Zerong He , Linfeng Tao , Xiaotian Wang , Letian Zhao , Zhaoxi Zeng , Wei Yuan , Wei Wu , Xi Jin

Multiplication is a core operation in modern neural network (NN) computations, contributing significantly to energy consumption. The linear-complexity multiplication (L-Mul) algorithm is specifically proposed as an approximate…

Hardware Architecture · Computer Science 2024-12-30 Ruiqi Chen , Yangxintong Lyu , Han Bao , Bruno da Silva

Deep neural networks (DNNs) have achieved great breakthroughs in many fields such as image classification and natural language processing. However, the execution of DNNs needs to conduct massive numbers of multiply-accumulate (MAC)…

Hardware Architecture · Computer Science 2024-11-07 Bo Liu , Grace Li Zhang , Xunzhao Yin , Ulf Schlichtmann , Bing Li

Large language models (LLMs) have shown impressive performance on language tasks but face challenges when deployed on resource-constrained devices due to their extensive parameters and reliance on dense multiplications, resulting in high…

Machine Learning · Computer Science 2024-11-20 Haoran You , Yipin Guo , Yichao Fu , Wei Zhou , Huihong Shi , Xiaofan Zhang , Souvik Kundu , Amir Yazdanbakhsh , Yingyan Celine Lin

Across a wide range of hardware scenarios, the computational efficiency and physical size of the arithmetic units significantly influence the speed and footprint of the overall hardware system. Nevertheless, the effectiveness of prior…

Machine Learning · Computer Science 2024-05-14 Yao Lai , Jinxin Liu , David Z. Pan , Ping Luo

Deploying Large Language Models (LLMs) on resource-constrained edge devices faces critical bottlenecks in memory bandwidth and power consumption. While ternary quantization (e.g., BitNet b1.58) significantly reduces model size, its direct…

Hardware Architecture · Computer Science 2026-05-05 Zi-Wei Lin , Tian-Sheuan Chang
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