Related papers: Analysis of Edge Mismatch and Output Power Degrada…
With scaling of Vt sub-threshold leakage power is increasing and expected to become significant part of total power consumption In present work three new configurations of level shifters for low power application in 0.35{\mu}m technology…
Modern applications such as energy harvesting, signal monitoring in bio-medical sensing, portable point of care devices, etc. which involve state of the art mixed signal subsystems require robust ultra low power operation. Here in this…
A novel topology for a high gain two-stage amplifier is proposed. The proposed circuit is designed in a way that the non-dominant pole is at output of the first stage. A positive capacitive feedback (PCF) around the second stage introduces…
Multilevel inverter converts different level DC voltage to AC voltage. It has wide interest in power industry especially in high power applications. In power electronic equipment the major drawback is the harmonics. Several control…
We present a power efficient clock-less fully asynchronous bit-serial Low Voltage Differential Signaling (LVDS) link with event-driven instant wake-up and self-sleep features, optimized for high speed inter-chip communication of…
This paper presents a low power, low jitter LC phase locked loop (PLL) which has been designed and fabricated in a commercial 0.25-um Silicon-on-Sapphire CMOS technology. Random jitter and deterministic jitter of the PLL are 1.3 ps and 7.5…
Hybrid distribution transformers (HDTs) integrate conventional transformers with partially rated power electronic converters to improve power quality, enable advanced ancillary services and increase penetration of renewable energy sources…
Previously, we demonstrated hysteretic and persistent changes of resistivity in two-terminal electronic devices based on charge trapping and detrapping at immobile metastable defects [H. Yin, A. Kumar, J.M. LeBeau, and R. Jaramillo, Phys.…
The operation of an integrated two-dimensional complementary metal-oxide-semiconductor inverter with well-matched input/output voltages is reported. The circuit combines a few-layer MoS2 n-MOSFET and a black phosphorus (BP) p-MOSFET…
A clock synchronizing circuit for repeaterless low swing interconnects is presented in this paper. The circuit uses a delay locked loop (DLL) to generate multiple phases of the clock, of which the one closest to the center of the eye is…
A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase shifter and a fine-phase shifter to achieve a step size of…
Low Power Design has become a significant requirement when the CMOS technology entered the nanometer era. Multiple-Supply Voltage (MSV) is a popular and effective method for both dynamic and static power reduction while maintaining…
A family of interleaved current-fed high step-up dc-dc converters are introduced and analyzed here by combining a voltage multiplier (VM) and an active clamp circuit for high-voltage high-power applications. Low input currents and output…
High-Level Synthesis (HLS) aspires to raise the level of abstraction in hardware design without sacrificing hardware efficiency. It has so far been successfully employed in signal and video processing but has found only limited use in other…
Multilevel inverters (MLIs) are popular because of their advantages such as improved output voltage quality, lower switching losses, low EMI, and ability to handle higher voltage and power levels. To generate the desired output voltage in…
In Part I, a method for the Harmonic Power-Flow (HPF) study of three-phase power grids with Converter-Interfaced Distributed Energy Resources (CIDERs) is proposed. The method is based on generic and modular representations of the grid and…
This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at 180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock frequency as compared to single edge triggered…
In this paper, a two-stage ultra-low-power operational amplifier is designed, and a comparative analysis of the proposed subthreshold complementary amplifier is presented between 180nm, 90nm, and 45nm CMOS technology. The proposed…
Clock generation is an essential part of wireless or wireline communication modules. To facilitate recent advancements in wireline-like communication and in-sensor computing modules at relatively lower data rates, ultra-low power, and…
A variable-phase-shifter (VPS) architecture with hybrid precoding for mixture use of phase shifters and switches, is proposed for millimeter wave massive multiple-input multiple-output communications. For the VPS architecture, a hybrid…