Related papers: A Time-Domain Dual-Edge Asynchronous Pipelined SAR…

This paper proposes and evaluates a novel architecture for a low-power Time-to-Digital Converter with high resolution, optimized for both integration in multichannel chips and high rate operation (40 Mconversion/s/channel). This converter…

A high-resolution time-to-digital converter (TDC) based on wave union (four-edge WU A), dual-sampling, and sub-TDL methods is proposed and implemented in a 16-nm Xilinx UltraScale+ field-programmable gate array (FPGA). We combine WU and…

Low-resolution analog-to-digital converters (ADCs) have emerged as a promising technology for reducing power consumption and complexity in massive multiple-input multiple-output (MIMO) systems while maintaining satisfactory spectral and…

Low-resolution digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) are considered to reduce cost and power consumption in multiuser massive multiple-input multiple-output (MIMO). Using the Bussgang theorem, we derive…

Conventional analog-to-digital converters (ADCs) fail to capture high-dynamic-range (HDR) signals due to clipping. Modulo ADCs circumvent this limitation by folding the input prior to quantization and algorithmically reconstructing the…

With the advent of the 5G wireless networks, achieving tens of gigabits per second throughputs and low, milliseconds, latency has become a reality. This level of performance will fuel numerous real-time applications, such as autonomy and…

A high-precision charge measurement can be achieved by the area integration of a digitized quasi-Gaussian signal after the signal passes through the shaper and analog-to-digital converter (ADC). The charge measurement contains an error due…

In this paper, we propose and evaluate a novel beamforming strategy for directional frame timing synchronization in wideband millimeter-wave (mmWave) systems operating with low-resolution analog-to-digital converters (ADCs). In the employed…

In this work we present numerical results concerning a time-delayed reservoir computing scheme, where its single nonlinear node, is a Quantum-Dot spin polarized Vertical Cavity Surface-Emitting Laser (QD s-VCSEL). The proposed photonic…

This manuscript describes a radiation-hardened current-mode delta-sigma ADC fabricated in a standard 130 nm CMOS technology and qualified for total ionizing doses up to 100 Mrad. The operational signal range achieved with a 100 s…

The characterization of laboratory plasma instabilities, magnetic reconnection and turbulence associated phenomena, require the simultaneous signal sampling from arrays of magnetic sensors (hundreds or even thousands) to obtain spatial…

We consider general multi-antenna fading channels with coarsely quantized outputs, where the channel is unknown to the transmitter and receiver. This analysis is of interest in the context of sensor network communication where low power and…

This paper considers the context of multiuser massive MIMO downlink precoding with low-resolution digital-to-analog converters (DACs) at the transmitter. This subject is motivated by the consideration that it is expensive to employ…

The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 micron CMOS process. On each of 6 analog…

We have developed a Time-to-Digital Converter (TDC) application in a Xilinx Kintex-7 Field Programmable Gate Array (FPGA). This TDC, based on the Tapped-Delay Line (TDL) and Wave Union A (WU-A) techniques, achieves an independent time…

Here in this paper we are presenting a digital system background technique for correcting the time offset error rate and gain mismatches in a time interleaved analog to digital converter system for N channel communication using 8 bit…

A 12 bit Pipeline ADC fabricated in a 0.18 $\mu$m pure digital CMOS technology is presented. Its nominal conversion rate is 110MS/s and the nominal supply voltage is 1.8V. The effective number of bits is 10.4 when a 10MHz input signal with…

In this work, the problem of signal parameter estimation from measurements acquired by a low-complexity analog-to-digital converter (ADC) with $1$-bit output resolution and an unknown quantization threshold is considered. Single-comparator…

Approximate computing is emerging as an alternative to accurate computing due to its potential for realizing digital circuits and systems with low power dissipation, less critical path delay, and less area occupancy for an acceptable…

A novel background calibration technique for Time-Interleaved Analog-to-Digital Converters (TI-ADCs) is presented in this paper. This technique is applicable to equalized digital communication receivers. As shown by Tsai et al. [1] and Luna…