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Recent years have witnessed remarkable advances in spatiotemporal predictive learning, with methods incorporating auxiliary inputs, complex neural architectures, and sophisticated training strategies. While SimVP has introduced a simpler,…

Machine Learning · Computer Science 2024-12-13 Cheng Tan , Zhangyang Gao , Siyuan Li , Stan Z. Li

Spiking Neural Networks (SNNs) offer a promising solution to the problem of increasing computational and energy requirements for modern Machine Learning (ML) applications. Due to their unique data representation choice of using spikes and…

Neural and Evolutionary Computing · Computer Science 2025-05-19 Daniel Windhager , Lothar Ratschbacher , Bernhard A. Moser , Michael Lunglmayr

DIFT (Dynamic Information Flow Tracking) has been a hot topic for more than a decade. Unfortunately, existing hardware DIFT approaches have not been widely used neither by research community nor by hardware vendors. It is due to two major…

Cryptography and Security · Computer Science 2018-12-05 Muhammad Abdul Wahab , Pascal Cotret , Mounir Nasr Allah , Guillaume Hiet , Arnab Kumar Biswas , Vianney Lapôtre , Guy Gogniat

Transposed Convolutions (TCONV) enable the up-scaling mechanism within generative Artificial Intelligence (AI) models. However, the predominant Input-Oriented Mapping (IOM) method for implementing TCONV has complex output mapping,…

Hardware Architecture · Computer Science 2025-07-11 Jude Haris , José Cano

Analog in-memory computing (AIMC) cores offers significant performance and energy benefits for neural network inference with respect to digital logic (e.g., CPUs). AIMCs accelerate matrix-vector multiplications, which dominate these…

To address increasing compute demand from recent multi-model workloads with heavy models like large language models, we propose to deploy heterogeneous chiplet-based multi-chip module (MCM)-based accelerators. We develop an advanced…

Hardware Architecture · Computer Science 2023-12-18 Mohanad Odema , Hyoukjun Kwon , Mohammad Abdullah Al Faruque

This project enables RISC-V microkernel support in IREE, an MLIR-based machine learning compiler and runtime. The approach begins by enabling the lowering of MLIR linalg dialect contraction ops to linalg.mmt4d op for the RISC-V64 target…

Hardware Architecture · Computer Science 2025-08-22 Adeel Ahmad , Ahmad Tameem Kamal , Nouman Amir , Bilal Zafar , Saad Bin Nasir

Vision-Language Models (VLMs) excel across diverse tasks but suffer from high inference costs in time and memory. Token sparsity mitigates inefficiencies in token usage, while neuron sparsity reduces high-dimensional computations, both…

Machine Learning · Computer Science 2025-05-27 Qinsi Wang , Hancheng Ye , Ming-Yu Chung , Yudong Liu , Yueqian Lin , Martin Kuo , Mingyuan Ma , Jianyi Zhang , Yiran Chen

While parallel architectures based on clusters of Processing Elements (PEs) sharing L1 memory are widespread, there is no consensus on how lean their PE should be. Architecting PEs as vector processors holds the promise to greatly reduce…

Hardware Architecture · Computer Science 2022-07-21 Matheus Cavalcante , Domenic Wüthrich , Matteo Perotti , Samuel Riedel , Luca Benini

Large Language Models (LLMs) are increasingly adopted for complex scientific text generation tasks, yet they often suffer from limitations in accuracy, consistency, and hallucination control. This thesis introduces a Parameter-Efficient…

Computation and Language · Computer Science 2024-11-12 Daniil Sulimov

The Adapteva Epiphany many-core architecture comprises a scalable 2D mesh Network-on-Chip (NoC) of low-power RISC cores with minimal uncore functionality. Whereas such a processor offers high computational energy efficiency and parallel…

Distributed, Parallel, and Cluster Computing · Computer Science 2017-04-28 David Richie , James Ross , Jamie Infantolino

As RISC-V architectures proliferate across embedded and high-performance domains, developers face persistent challenges in performance optimization due to fragmented tooling, immature hardware features, and platform-specific defects. This…

Performance · Computer Science 2025-07-31 Alexander Batashev

The fast proliferation of extreme-edge applications using Deep Learning (DL) based algorithms required dedicated hardware to satisfy extreme-edge applications' latency, throughput, and precision requirements. While inference is achievable…

Hardware Architecture · Computer Science 2022-04-26 Yvan Tortorella , Luca Bertaccini , Davide Rossi , Luca Benini , Francesco Conti

Radio Resource Management (RRM) in 5G mobile communication is a challenging problem for which Recurrent Neural Networks (RNN) have shown promising results. Accelerating the compute-intensive RNN inference is therefore of utmost importance.…

Signal Processing · Electrical Eng. & Systems 2020-04-07 Renzo Andri , Tomas Henriksson , Luca Benini

Open-source RISC-V cores are increasingly adopted in high-end embedded domains such as automotive, where maximizing instructions per cycle (IPC) is becoming critical. Building on the industry-supported open-source CVA6 core and its…

Earth system models are developed with a tight coupling to target hardware, often containing specialized code predicated on processor characteristics. This coupling stems from using imperative languages that hard-code computation schedules…

It is demonstrated how the non-proprietary OpenACC standard of compiler directives may be used to compactly and efficiently accelerate the rate-determining steps of two of the most routinely applied many-body methods of electronic structure…

Chemical Physics · Physics 2017-09-15 Janus Juul Eriksen

We present the acceleration of an IMplicit-EXplicit (IMEX) non-hydrostatic atmospheric model on manycore processors such as GPUs and Intel's MIC architecture. IMEX time integration methods sidestep the constraint imposed by the…

Sparse matrix-vector multiplication (SpMV) is a fundamental operation in machine learning, scientific computing, and graph algorithms. In this paper, we investigate the space, time, and energy efficiency of SpMV using various compressed…

Data Structures and Algorithms · Computer Science 2024-09-30 Francesco Tosoni , Philip Bille , Valerio Brunacci , Alessio De Angelis , Paolo Ferragina , Giovanni Manzini

The rapid growth of AI-based Internet-of-Things applications increased the demand for high-performance edge processing engines on a low-power budget and tight area constraints. As a consequence, vector processor architectures, traditionally…