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Recent advancements in code generation have shown remarkable success across software domains, yet hardware description languages (HDLs) such as Verilog remain underexplored due to their concurrency semantics, syntactic rigidity, and…

Machine Learning · Computer Science 2025-08-27 Fu Teng , Miao Pan , Xuhong Zhang , Zhezhi He , Yiyao Yang , Xinyi Chai , Mengnan Qi , Liqiang Lu , Jianwei Yin

The deployment of Machine Learning (ML) applications at the edge on resource-constrained devices has accentuated the need for efficient ML processing on low-cost processors. While traditional CPUs provide programming flexibility, their…

Hardware Architecture · Computer Science 2025-03-25 Vasileios Titopoulos , George Alexakis , Kosmas Alexandridis , Chrysostomos Nicopoulos , Giorgos Dimitrakopoulos

Remote sensing (RS) large vision-language models (LVLMs) have shown strong promise across visual grounding (VG) tasks. However, existing RS VG datasets predominantly rely on explicit referring expressions-such as relative position, relative…

Computer Vision and Pattern Recognition · Computer Science 2026-01-06 Yue Zhou , Jue Chen , Zilun Zhang , Penghui Huang , Ran Ding , Zhentao Zou , PengFei Gao , Yuchen Wei , Ke Li , Xue Yang , Xue Jiang , Hongxin Yang , Jonathan Li

Visual reasoning, the capability to interpret visual input in response to implicit text query through multi-step reasoning, remains a challenge for deep learning models due to the lack of relevant benchmarks. Previous work in visual…

Computer Vision and Pattern Recognition · Computer Science 2025-05-20 Yiqing Shen , Chenjia Li , Chenxiao Fan , Mathias Unberath

Address translation and protection play important roles in today's processors, supporting multiprocessing and enforcing security. Historically, the design of the address translation mechanisms has been closely tied to the instruction set.…

Hardware Architecture · Computer Science 2019-05-17 Xuan Guo , Robert Mullins

RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as…

Hardware Architecture · Computer Science 2020-12-30 Hiromu Miyazaki , Takuto Kanamori , Md Ashraful Islam , Kenji Kise

The emergence and rapid development of the open RISC-V instruction set architecture opens up new horizons on the way to efficient devices, ranging from existing low-power IoT boards to future high-performance servers. The effective use of…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-04-04 Evgeny Kozinov , Evgeny Vasiliev , Andrey Gorshkov , Valentina Kustikova , Artem Maklaev , Valentin Volokitin , Iosif Meyerov

Considering the high-performance and low-power requirements of edge AI, this study designs a specialized instruction set processor for edge AI based on the RISC-V instruction set architecture, addressing practical issues in digital signal…

Hardware Architecture · Computer Science 2024-09-04 Xu-Hao Chen , Si-Peng Hu , Hong-Chao Liu , Bo-Ran Liu , Dan Tang , Di Zhao

Large Language Models (LLMs) have advanced Verilog code generation significantly, yet face challenges in data quality, reasoning capabilities, and computational efficiency. This paper presents ReasoningV, a novel model employing a hybrid…

Hardware Architecture · Computer Science 2025-05-02 Haiyan Qin , Zhiwei Xie , Jingjing Li , Liangchen Li , Xiaotong Feng , Junzhan Liu , Wang Kang

The rapid growth of Large Language Models (LLMs) and AI-driven applications has propelled Vector Database Management Systems (VDBMSs) into the spotlight as a critical infrastructure component. VDBMS specializes in storing, indexing, and…

Software Engineering · Computer Science 2025-03-03 Shenao Wang , Yanjie Zhao , Yinglin Xie , Zhao Liu , Xinyi Hou , Quanchen Zou , Haoyu Wang

Large Language Models (LLMs) have demonstrated remarkable capabilities in code generation, but their proficiency in producing secure code remains a critical, under-explored area. Existing benchmarks often fall short by relying on synthetic…

Cryptography and Security · Computer Science 2026-02-02 Yanlin Wang , Ziyao Zhang , Chong Wang , Xinyi Xu , Mingwei Liu , Yong Wang , Jiachi Chen , Zibin Zheng

In intra coding, Rate Distortion Optimization (RDO) is performed to achieve the optimal intra mode from a pre-defined candidate list. The optimal intra mode is also required to be encoded and transmitted to the decoder side besides the…

Image and Video Processing · Electrical Eng. & Systems 2022-04-11 Linwei Zhu , Yun Zhang , Na Li , Gangyi Jiang , Sam Kwong

Scalable Vector Graphics (SVG) are central to digital design due to their inherent scalability and editability. Despite significant advancements in content generation enabled by Visual Language Models (VLMs), existing text-to-SVG generation…

Computer Vision and Pattern Recognition · Computer Science 2026-03-11 Feiyu Wang , Jiayuan Yang , Zhiyuan Zhao , Da Zhang , Bingyu Li , Peng Liu , Junyu Gao

Wireless baseband processing (WBP) serves as an ideal scenario for utilizing vector processing, which excels in managing data-parallel operations due to its parallel structure. However, conventional vector architectures face certain…

Hardware Architecture · Computer Science 2025-09-09 Limin Jiang , Yi Shi , Yihao Shen , Shan Cao , Zhiyuan Jiang , Sheng Zhou

Structured sparsity has been proposed as an efficient way to prune the complexity of modern Machine Learning (ML) applications and to simplify the handling of sparse data in hardware. The acceleration of ML models - for both training and…

Hardware Architecture · Computer Science 2023-11-14 V. Titopoulos , K. Alexandridis , C. Peltekis , C. Nicopoulos , G. Dimitrakopoulos

Merge sort as a divide-sort-merge paradigm has been widely applied in computer science fields. As modern reduced instruction set computing architectures like the fifth generation (RISC-V) regard multiple registers as a vector register group…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-10-02 Jin Zhang , Jincheng Zhou , Xiang Zhang , Di Ma , Chunye Gong

The rise of hardware accelerators with custom instructions necessitates custom compiler backends supporting these accelerators. This study provides detailed analyses of LLVM and its RISC-V backend, supplemented with case studies providing…

Hardware Architecture · Computer Science 2023-10-31 Eymen Ünay , Bora İnan , Emrecan Yiğit

With the unprecedented advancements in Large Language Models (LLMs), their application domains have expanded to include code generation tasks across various programming languages. While significant progress has been made in enhancing LLMs…

Software Engineering · Computer Science 2024-06-10 Prashanth Vijayaraghavan , Luyao Shi , Stefano Ambrogio , Charles Mackin , Apoorva Nitsure , David Beymer , Ehsan Degan

For years, SIMD/vector units have enhanced the capabilities of modern CPUs in High-Performance Computing (HPC) and mobile technology. Typical commercially-available SIMD units process up to 8 double-precision elements with one instruction.…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-11-14 Pablo Vizcaino , Georgios Ieronymakis , Nikolaos Dimou , Vassilis Papaefstathiou , Jesus Labarta , Filippo Mantovani

Embedded systems are pervasively used in many fields nowadays. In mixed-criticality environments (automotive, industry 4.0, drones, etc.) they need to run real-time applications with certain time and safety constraints alongside a rich…

Cryptography and Security · Computer Science 2021-11-05 Flavia Caforio , Pierpaolo Iannicelli , Michele Paolino , Daniel Raho