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In this paper, we propose TAPA, an end-to-end framework that compiles a C++ task-parallel dataflow program into a high-frequency FPGA accelerator. Compared to existing solutions, TAPA has two major advantages. First, TAPA provides a set of…

Hardware Architecture · Computer Science 2024-10-18 Licheng Guo , Yuze Chi , Jason Lau , Linghao Song , Xingyu Tian , Moazin Khatti , Weikang Qiao , Jie Wang , Ecenur Ustun , Zhenman Fang , Zhiru Zhang , Jason Cong

GPU architectures have continued to grow in complexity, with recent incarnations introducing increasingly powerful fixed-function units for matrix multiplication and data movement to accompany highly parallel general-purpose cores. To fully…

Programming Languages · Computer Science 2025-12-23 Rupanshu Soi , Rohan Yadav , Fredrik Kjolstad , Alex Aiken , Maryam Mehri Dehnavi , Michael Garland , Michael Bauer

Static timing analysis (STA) is crucial for Electronic Design Automation (EDA) flows but remains a computational bottleneck. While existing GPU-based STA engines are faster than CPU, they suffer from inefficiencies, particularly intra-warp…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-03-31 En-Ming Huang , Shih-Hao Hung

Modern transformer-based deep neural networks present unique technical challenges for effective acceleration in real-world applications. Apart from the vast amount of linear operations needed due to their sizes, modern transformer models…

Hardware Architecture · Computer Science 2024-11-07 Jiajun Wu , Mo Song , Jingmin Zhao , Yizhao Gao , Jia Li , Hayden Kwok-Hay So

As Large Language Models (LLMs) scale to handle massive concurrent traffic, optimizing the infrastructure required for inference has become a primary challenge. To manage the high cost of GPU resources while ensuring strict service-level…

Contemporary GPUs are designed to handle long-latency operations effectively; however, challenges such as core occupancy (number of warps in a core) and pipeline width can impede their latency management. This is particularly evident in…

Hardware Architecture · Computer Science 2024-04-10 Diya Joseph , Juan Luis Aragón , Joan-Manuel Parcerisa , Antonio Gonzalez

In the era of LLMs, dense operations such as GEMM and MHA are critical components. These operations are well-suited for parallel execution using a tilebased approach. While traditional GPU programming often relies on low level interfaces…

Computation and Language · Computer Science 2025-03-27 Dewei Wang , Wei Zhu , Liyang Ling , Ettore Tiotto , Quintin Wang , Whitney Tsang , Julian Opperman , Jacky Deng

Recent deep learning workloads increasingly push computational demand beyond what current memory systems can sustain, with many kernels stalling on data movement rather than computation. While modern dataflow accelerators incorporate…

Programming Languages · Computer Science 2025-09-09 Shihan Fang , Hongzheng Chen , Niansong Zhang , Jiajie Li , Han Meng , Adrian Liu , Zhiru Zhang

Benefiting from the self-attention mechanism, Transformer models have attained impressive contextual comprehension capabilities for lengthy texts. The requirements of high-throughput inference arise as the large language models (LLMs)…

Hardware Architecture · Computer Science 2024-07-16 Huizheng Wang , Jiahao Fang , Xinru Tang , Zhiheng Yue , Jinxi Li , Yubin Qin , Sihan Guan , Qize Yang , Yang Wang , Chao Li , Yang Hu , Shouyi Yin

Modern Graphics Processing Units (GPUs) are well provisioned to support the concurrent execution of thousands of threads. Unfortunately, different bottlenecks during execution and heterogeneous application requirements create imbalances in…

Computationally intensive Inference tasks of Deep neural networks have enforced revolution of new accelerator architecture to reduce power consumption as well as latency. The key figure of merit in hardware inference accelerators is the…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-09-11 Hyunbin Park , Dohyun Kim , Shiho Kim

To efficiently support Large Language Models (LLMs), modern GPGPU architectures have introduced new features and programming paradigms, such as warp specialization. These features enable temporal overlap between the producer and consumer,…

Hardware Architecture · Computer Science 2026-05-05 Zhongchun Zhou , Yuhang Gu , Chengtao Lai , Ya Wang , Wei Zhang

The performance of graph programs depends highly on the algorithm, the size and structure of the input graphs, as well as the features of the underlying hardware. No single set of optimizations or one hardware platform works well across all…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-01-11 Ajay Brahmakshatriya , Yunming Zhang , Changwan Hong , Shoaib Kamil , Julian Shun , Saman Amarasinghe

Vision Transformers (ViTs) excel in computer vision tasks but lack flexibility for edge devices' diverse needs. A vital issue is that ViTs pre-trained to cover a broad range of tasks are \textit{over-qualified} for edge devices that usually…

Computer Vision and Pattern Recognition · Computer Science 2025-04-07 Ziteng Wei , Qiang He , Bing Li , Feifei Chen , Yun Yang

Despite the increasing adoption of Field-Programmable Gate Arrays (FPGAs) in compute clouds, there remains a significant gap in programming tools and abstractions which can leverage network-connected, cloud-scale, multi-die FPGAs to…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-02-05 Neha Prakriya , Yuze Chi , Suhail Basalama , Linghao Song , Jason Cong

The MWA is a next-generation radio interferometer under construction in remote Western Australia. The data rate from the correlator makes storing the raw data infeasible, so the data must be processed in real-time. The processing task is of…

Instrumentation and Methods for Astrophysics · Physics 2009-02-06 S. Ord , L. Greenhill , R. Wayth , D. Mitchell , K. Dale , H. Pfister , R. G. Edgar

Deep neural networks (DNNs) have emerged as successful solutions for variety of artificial intelligence applications, but their very large and deep models impose high computational requirements during training. Multi-GPU parallelization is…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-02-08 Sungho Shin , Youngmin Jo , Jungwook Choi , Swagath Venkataramani , Vijayalakshmi Srinivasan , Wonyong Sung

Domain-specific, fixed-function units are becoming increasingly common in modern processors. As the computational demands of applications evolve, the capabilities and programming interfaces of these fixed-function units continue to change.…

Programming Languages · Computer Science 2025-04-10 Rohan Yadav , Michael Garland , Alex Aiken , Michael Bauer

Time Series Analysis (TSA) is a critical workload to extract valuable information from collections of sequential data, e.g., detecting anomalies in electrocardiograms. Subsequence Dynamic Time Warping (sDTW) is the state-of-the-art…

Serving Large Language Models (LLMs) is critical for AI-powered applications, yet it demands substantial computational resources, particularly in memory bandwidth and computational throughput. Low-precision computation has emerged as a key…

Machine Learning · Computer Science 2025-09-03 Yaoyao Ding , Bohan Hou , Xiao Zhang , Allan Lin , Tianqi Chen , Cody Yu Hao , Yida Wang , Gennady Pekhimenko
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