English
Related papers

Related papers: SAHM: State-Aware Heterogeneous Multicore for Sing…

200 papers

The development of Cloud-Edge-IoT applications requires robust programming models. Existing models often struggle to manage the dynamic and stateful nature of these applications effectively. This paper introduces the Collaborative State…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-07-30 Marlon Etheredge , Thomas Fahringer , Felix Erlacher , Elias Kohler , Stefan Pedratscher , Juan Aznar-Poveda , Nishant Saurabh , Adrien Lebre

Multi-core processors improve performance, but they can create unpredictability owing to shared resources such as caches interfering. Cache partitioning is used to alleviate the Worst-Case Execution Time (WCET) estimation by isolating the…

Hardware Architecture · Computer Science 2022-01-28 Soma N. Ghosh , Vineet Sahula , Lava Bhargava

We propose Atomic Active Messages (AAM), a mechanism that accelerates irregular graph computations on both shared- and distributed-memory machines. The key idea behind AAM is that hardware transactional memory (HTM) can be used for simple…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-11-02 Maciej Besta , Torsten Hoefler

Reliability has emerged as a key topic of interest for researchers around the world to detect and/or mitigate the side effects of decreasing transistor sizes, such as soft errors. Traditional solutions, like DMR and TMR, incur significant…

Hardware Architecture · Computer Science 2019-10-22 Bharath Srinivas Prabakaran , Mihika Dave , Florian Kriebel , Semeen Rehman , Muhammad Shafique

To support emerging mobile use cases (e.g., AR/VR, autonomous driving, and massive IoT), next-generation mobile cores for 5G and 6G are being re-architected as service-based architectures (SBAs) running on both private and public clouds.…

Networking and Internet Architecture · Computer Science 2025-09-10 Bilal Saleem , Omar Basit , Jiayi Meng , Iftekhar Alam , Ajay Thakur , Christian Maciocco , Muhammad Shahbaz , Y. Charlie Hu , Larry Peterson

Modern applications process massive data volumes that overwhelm the storage and retrieval capabilities of memory systems, making memory the primary performance and energy-efficiency bottleneck of computing systems. Although many…

Hardware Architecture · Computer Science 2026-03-10 Rahul Bera

Scaling pre-trained language models has resulted in large performance gains in various natural language processing tasks but comes with a large cost in memory requirements. Inspired by the position embeddings in transformers, we aim to…

Computation and Language · Computer Science 2023-10-13 Huiyin Xue , Nikolaos Aletras

Runtime resource management for many-core systems is increasingly complex. The complexity can be due to diverse workload characteristics with conflicting demands, or limited shared resources such as memory bandwidth and power. Resource…

Hardware Architecture · Computer Science 2020-08-04 Bryan Donyanavard , Amir M. Rahmani , Axel Jantsch , Onur Mutlu , Nikil Dutt

Graph Neural Networks (GNNs) have shown success in many real-world applications that involve graph-structured data. Most of the existing single-node GNN training systems are capable of training medium-scale graphs with tens of millions of…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-03-02 Yi-Chien Lin , Viktor Prasanna

This paper summarizes our work on characterizing application memory error vulnerability to optimize datacenter cost via Heterogeneous-Reliability Memory (HRM), which was published in DSN 2014, and examines the work's significance and future…

Distributed, Parallel, and Cluster Computing · Computer Science 2018-05-11 Yixin Luo , Sriram Govindan , Bikash Sharma , Mark Santaniello , Justin Meza , Aman Kansal , Jie Liu , Badriddine Khessib , Kushagra Vaid , Onur Mutlu

As the amount of data produced in society continues to grow at an exponential rate, modern applications are incurring significant performance and energy penalties due to high data movement between the CPU and memory/storage. While…

Hardware Architecture · Computer Science 2024-03-12 Ryan Wong , Nikita Kim , Kevin Higgs , Sapan Agarwal , Engin Ipek , Saugata Ghose , Ben Feinberg

Attention and State-Space Models (SSMs) when combined in a hybrid network in sequence or in parallel provide complementary strengths. In a hybrid sequential pipeline they alternate between applying a transformer to the input and then…

Computation and Language · Computer Science 2025-05-29 Mohammad Mahdi Moradi , Walid Ahmed , Shuangyue Wen , Sudhir Mudur , Weiwei Zhang , Yang Liu

State Space Models (SSMs) have emerged as powerful architectures in computer vision, yet improving their computational efficiency remains crucial for practical and scalable deployment.While token reduction serves as an effective approach…

Computer Vision and Pattern Recognition · Computer Science 2025-08-20 Jinyoung Park , Minseok Son , Changick Kim

The well known method C-Slow Retiming (CSR) can be used to automatically convert a given CPU into a multithreaded CPU with independent threads. These CPUs are then called streaming or barrel processors. System Hyper Pipelining (SHP) adds a…

Hardware Architecture · Computer Science 2015-08-31 Tobias Strauch

The analysis of massive scientific data often happens in the form of workflows with interdependent tasks. When such a scientific workflow needs to be scheduled on a parallel or distributed system, one usually represents the workflow as a…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-03-31 Svetlana Kulagina , Anne Benoit , Henning Meyerhenke

Dynamic neural networks (DyNNs) have become viable techniques to enable intelligence on resource-constrained edge devices while maintaining computational efficiency. In many cases, the implementation of DyNNs can be sub-optimal due to its…

Machine Learning · Computer Science 2022-12-08 Halima Bouzidi , Mohanad Odema , Hamza Ouarnoughi , Mohammad Abdullah Al Faruque , Smail Niar

Relaxed retention (or volatile) spin-transfer torque RAM (STT-RAM) has been widely studied as a way to reduce STT-RAM's write energy and latency overheads. Given a relaxed retention time STT-RAM level one (L1) cache, we analyze the impacts…

Computers and Society · Computer Science 2024-07-30 Dhruv Gajaria , Tosiron Adegbija

Massive multi-threading in GPU imposes tremendous pressure on memory subsystems. Due to rapid growth in thread-level parallelism of GPU and slowly improved peak memory bandwidth, the memory becomes a bottleneck of GPU's performance and…

Hardware Architecture · Computer Science 2019-06-17 Bing Li , Mengjie Mao , Xiaoxiao Liu , Tao Liu , Zihao Liu , Wujie Wen , Yiran Chen , Hai , Li

Modern data centers and cloud computing clusters are increasingly running workloads composed of malleable jobs. A malleable job can be parallelized across any number of cores, yet the job typically exhibits diminishing marginal returns for…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-02-03 Zhouzi Li , Mor Harchol-Balter , Benjamin Berg

As multicore systems continue to scale, cache coherence has emerged as a critical determinant of system performance, with coherence behavior and task execution closely intertwined, reshaping inter-task dependencies. Task graph modeling…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-09-12 Guochu Xiong , Xiangzhong Luo , Weichen Liu
‹ Prev 1 8 9 10 Next ›