Related papers: Implementation of a 8-bit Wallace Tree Multiplier
We present a modular atom-array quantum computing architecture with space-time hybrid multiplexing (MAQCY), a dynamic optical tweezer-based protocol for fully connected and scalable universal quantum computation. By extending the concept of…
The memristor is promising to be the basic cell of next-generation computation systems. Compared to the traditional MOSFET device, the memristor is efficient over energy and area. But one of the biggest challenges faced with researchers is…
Full binary trees naturally represent commutative non-associative products. There are many important examples of these products: finite-precision floating-point addition and NAND gates, among others. Balance in such a tree is highly…
Priority encoders are typically considered expensive hardware components in terms of complexity, especially at high bit precisions or input lengths (e.g., above 512 bits). However, if the complexity can be reduced, priority encoders can…
This paper proposes a Low-Power, Energy Efficient 4-bit Binary Coded Decimal (BCD) adder design where the conventional 4-bit BCD adder has been modified with the Clock Gated Power Gating Technique. Moreover, the concept of DVT (Dual-vth)…
Future wireless networks are envisioned to employ multiple-input multiple-output (MIMO) transmissions with large array sizes, and therefore, the adoption of complexity-scalable transceiver becomes important. In this paper, we propose a…
Recent research on multilevel inverters shows exciting properties, including the potential to generate multiple output voltages and integrated voltage boosting. However, most presented inverter topologies have a restricted number of output…
The rapidly increasing size of deep-learning models has caused renewed and growing interest in alternatives to digital computers to dramatically reduce the energy cost of running state-of-the-art neural networks. Optical matrix-vector…
In our work we analyze computational aspects of the problem of numerical integration in finite element calculations and consider an OpenCL implementation of related algorithms for processors with wide vector registers. As a platform for…
Time-Division Multiplexing is the readout architecture of choice for many ground and space experiments, as it is a very mature technology with proven outstanding low-frequency noise stability, which represents a central challenge in…
This paper presents an in-memory computing (IMC) architecture developed on an 8x8 array of 8T SRAM cells. This architecture enables both multi-bit parallel Multiply-Accumulate (MAC) operations and standard memory processing through…
Computing problems that handle large amounts of data necessitate the use of lossless data compression for efficient storage and transmission. We present a novel lossless universal data compression algorithm that uses parallel computational…
Research in the field of low-temperature electronics is limited by the small number of electrical contacts available on cryogenic set ups. This not only restricts the number of devices that can be fabricated, but also the device and circuit…
Monte Carlo Tree Search (MCTS) is an effective test-time compute scaling (TTCS) method for improving the reasoning performance of large language models, but its highly variable execution time leads to severe long-tail latency in practice.…
In the search for improved computational capabilities, conventional microelectronic computers are facing various problems arising from the miniaturization and concentration of active electronics devices (1-2). Therefore, researchers have…
An analog integrated circuit has been designed, in a BiCMOS 0.8 micron technology, for the feasability study of the signal processing of the AMS RICH photomultiplier tubes. This low power, three channel gated integrator includes its own…
Matrix multiplications between asymmetric bit-width operands, especially between 8- and 4-bit operands are likely to become a fundamental kernel of many important workloads including neural networks and machine learning. While existing SIMD…
The whole computer hardware industry embraced multicores. For these machines, the extreme optimisation of sequential algorithms is no longer sufficient to squeeze the real machine power, which can be only exploited via thread-level…
Linear-scaling electronic-structure techniques, also called O(N) techniques, rely heavily on the multiplication of sparse matrices, where the sparsity arises from spatial cut-offs. In order to treat very large systems, the calculations must…
Building upon previously introduced Bistable Vortex Memory (BVM) as a novel, nonvolatile, high-density, and scalable superconductor memory technology, this work presents a methodology that uses BVM arrays to address challenges in…