English
Related papers

Related papers: Implementation of a 8-bit Wallace Tree Multiplier

200 papers

The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators.…

Signal Processing · Electrical Eng. & Systems 2018-08-09 Rozita Teymourzadeh , Yazan Samir , Masuri Othman , Mok Vee Hong

Transformers have revolutionized AI in natural language processing and computer vision, but their large computation and memory demands pose major challenges for hardware acceleration. In practice, end-to-end throughput is often limited by…

Hardware Architecture · Computer Science 2026-03-20 Qunyou Liu , Marina Zapater , David Atienza

Decision trees are highly famous in machine learning and usually acquire state-of-the-art performance. Despite that, well-known variants like CART, ID3, random forest, and boosted trees miss a probabilistic version that encodes prior…

Artificial Intelligence · Computer Science 2022-07-27 Efthyvoulos Drousiotis , Paul G. Spirakis

Versatile Video Coding (VVC) is the next generation video coding standard expected by the end of 2020. Compared to its predecessor, VVC introduces new coding tools to make compression more efficient at the expense of higher computational…

Image and Video Processing · Electrical Eng. & Systems 2020-02-19 I. Farhat , W. Hamidouche , A Grill , D. Ménard , O. Deforges

In this paper, we present a multiplier based on a sequence of approximated accumulations. According to a given splitting point of the carry chains, the technique herein introduced allows varying the quality of the accumulations and,…

Hardware Architecture · Computer Science 2021-05-26 Jorge Echavarria , Stefan Wildermann , Oliver Keszocze , Faramarz Khosravi , Andreas Becher , Jürgen Teich

As IoT and edge inference proliferate,there is a growing need to simultaneously optimize area and delay in lookup-table (LUT)-based multipliers that implement large numbers of low-bitwidth operations in parallel. This paper proposes a…

Hardware Architecture · Computer Science 2025-10-27 Misaki Kida , Shimpei Sato

The Cerebras Wafer-Scale Engine (WSE) delivers performance at an unprecedented scale of over 900,000 compute units, all connected via a single-wafer on-chip interconnect. Initially designed for AI, the WSE architecture is also well-suited…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-01-27 Nicolai Stawinoga , David Katz , Anton Lydike , Justs Zarins , Nick Brown , George Bisbas , Tobias Grosser

Elliptic Curve Cryptography (ECC) is widely accepted for ensuring secure data exchange between resource-limited IoT devices. The National Institute of Standards and Technology (NIST) recommended implementation, such as B-163, is…

Hardware Architecture · Computer Science 2025-06-17 Ruby Kumari , Tapas Rout , Babul Saini , Jai Gopal Pandey , Abhijit Karmakar

General matrix-matrix multiplication (GEMM) is a cornerstone of AI computations, making tensor processing engines (TPEs) increasingly critical in GPUs and domain-specific architectures. Existing architectures primarily optimize dataflow or…

Hardware Architecture · Computer Science 2025-03-11 Qizhe Wu , Huawen Liang , Yuchen Gui , Zhichen Zeng , Zerong He , Linfeng Tao , Xiaotian Wang , Letian Zhao , Zhaoxi Zeng , Wei Yuan , Wei Wu , Xi Jin

Elliptic curve cryptography (ECC) is widely used in security applications such as public key cryptography (PKC) and zero-knowledge proofs (ZKP). ECC is composed of modular arithmetic, where modular multiplication takes most of the…

Hardware Architecture · Computer Science 2024-02-23 Jonathan Ku , Junyao Zhang , Haoxuan Shan , Saichand Samudrala , Jiawen Wu , Qilin Zheng , Ziru Li , JV Rajendran , Yiran Chen

Today every circuit has to face the power consumption issue for both portable device aiming at large battery life and high end circuits avoiding cooling packages and reliability issues that are too complex. It is generally accepted that…

Hardware Architecture · Computer Science 2010-07-15 C. N. Marimuthu , P. Thangaraj , Aswathy Ramesan

Quantum-dot Cellular Automata (QCA) is one of the most important computing technologies for the future and will be the alternative candidate for current CMOS technology. QCA is attracting a lot of researchers due to many features such as…

Emerging Technologies · Computer Science 2020-02-04 Esam Alkaldy , Ali H. Majeed , Mohd Shamian Zainal , Danial Md. Nor

In this paper a low power and low area array multiplier with carry save adder is proposed. The proposed adder eliminates the final addition stage of the multiplier than the conventional parallel array multiplier. The conventional and…

Hardware Architecture · Computer Science 2011-12-01 Nirlakalla Ravi , A. Satish , T. Jayachandra Prasad , T. Subba Rao

The Advanced Encryption Standard (AES) algorithm is a symmetric block cipher which operates on a sequence of blocks each consists of 128, 192 or 256 bits. Moreover, the cipher key for the AES algorithm is a sequence of 128, 192 or 256 bits.…

Cryptography and Security · Computer Science 2015-01-08 Ghada F. Elkabbany , Heba K. Aslan , Mohamed N. Rasslan

In this paper we present a hardware-oriented algorithm for constant matrix-vector product calculating, when the all elements of vector and matrix are complex numbers. The proposed algorithm versus the naive method of analogous calculations…

Data Structures and Algorithms · Computer Science 2014-10-28 Aleksandr Cariow , Galina Cariowa

The Cavallo multiplier [http://archive.org/details/b28771035_0003] is an electrostatic inductance machine that can generate low-noise high voltages electrically isolated from its voltage input, making it ideally suited for precision…

Multiplication is a basic arithmetic operation that is encountered in almost all general-purpose microprocessing and digital signal processing applications, and multiplication is physically realized using a multiplier. This paper discusses…

Hardware Architecture · Computer Science 2019-05-28 P Balasubramanian , D L Maskell , N E Mastorakis

Electronic devices primarily aim to offer low power consumption, high speed, and a compact area. The performance of very large-scale integration (VLSI) devices is influenced by arithmetic operations, where multiplication is a crucial…

Hardware Architecture · Computer Science 2025-06-16 Ali Ranjbar , Elham Esmaeili , Roghayeh Rafieisangari , Nabiollah Shiri

Finite field multiplier is mainly used in error-correcting codes and signal processing. Finite field multiplier is regarded as the bottleneck arithmetic unit for such applications and it is the most complicated operation over finite field…

Information Theory · Computer Science 2023-09-15 Saeideh Nabipour , Gholamreza Zare Fatin , Javad Javidan

The wavelet tree (Grossi et al. [SODA, 2003]) and wavelet matrix (Claude et al. [Inf. Syst., 47:15--32, 2015]) are compact indices for texts over an alphabet $[0,\sigma)$ that support rank, select and access queries in $O(\lg \sigma)$ time.…

Data Structures and Algorithms · Computer Science 2017-11-13 Johannes Fischer , Florian Kurpicz , Marvin Löbel