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Cutting-edge embedded system applications, such as self-driving cars and unmanned drone software, are reliant on integrated CPU/GPU platforms for their DNNs-driven workload, such as perception and other highly parallel components. In this…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-03-20 Soroush Bateni , Zhendong Wang , Yuankun Zhu , Yang Hu , Cong Liu

The past year has witnessed the increasing popularity of Large Language Models (LLMs). Their unprecedented scale and associated high hardware cost have impeded their broader adoption, calling for efficient hardware designs. With the large…

Hardware Architecture · Computer Science 2023-12-07 Hengrui Zhang , August Ning , Rohan Prabhakar , David Wentzlaff

The growing demand for optimal and low-power energy consumption paradigms for IOT devices has garnered significant attention due to their cost-effectiveness, simplicity, and intelligibility. In this article, an AI hardware energy-efficient…

Signal Processing · Electrical Eng. & Systems 2024-12-03 Zheqi Yu , Chao Zhang , Pedro Machado , Adnan Zahid , Tim. Fernandez-Hart , Muhammad A. Imran , Qammer H. Abbasi

Deep functional map frameworks are widely employed for 3D shape matching. However, most existing deep functional map methods cannot adaptively capture important frequency information for functional map estimation in specific matching…

Computer Vision and Pattern Recognition · Computer Science 2024-06-26 Feifan Luo , Qinsong Li , Ling Hu , Haibo Wang , Xinru Liu , Shengjun Liu , Hongyang Chen

Neuromorphic Multiply-And-Accumulate (MAC) circuits utilizing synaptic weight elements based on SRAM or novel Non-Volatile Memories (NVMs) provide a promising approach for highly efficient hardware representations of neural networks. NVM…

Emerging Technologies · Computer Science 2018-09-14 Borna Obradovic , Titash Rakshit , Ryan Hatcher , Jorge A. Kittl , Mark S. Rodder

Hardware accelerators such as GPUs are required for real-time, low-latency inference with Deep Neural Networks (DNN). However, due to the inherent limits to the parallelism they can exploit, DNNs often under-utilize the capacity of today's…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-04-27 Aditya Dhakal , Sameer G. Kulkarni , K. K. Ramakrishnan

Distributed execution of deep learning training involves a dynamic interplay between hardware accelerator architecture and device placement strategy. This is the first work to explore the co-optimization of determining the optimal…

Machine Learning · Computer Science 2024-07-19 Irene Wang , Jakub Tarnawski , Amar Phanishayee , Divya Mahajan

Deep learning has emerged as a powerful method for extracting valuable information from large volumes of data. However, when new training data arrives continuously (i.e., is not fully available from the beginning), incremental training…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-06-06 Thomas Bouvier , Bogdan Nicolae , Hugo Chaugier , Alexandru Costan , Ian Foster , Gabriel Antoniu

This study proposes a hybrid deep-learning-metaheuristic framework with a bi-level architecture for road network design problems (NDPs). We train a graph neural network (GNN) to approximate the solution of the user equilibrium (UE) traffic…

Neural and Evolutionary Computing · Computer Science 2023-12-12 Bahman Madadi , Goncalo Homem de Almeida Correia

Deep neural networks (DNNs) have emerged as successful solutions for variety of artificial intelligence applications, but their very large and deep models impose high computational requirements during training. Multi-GPU parallelization is…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-02-08 Sungho Shin , Youngmin Jo , Jungwook Choi , Swagath Venkataramani , Vijayalakshmi Srinivasan , Wonyong Sung

Deep neural network (DNN) inference is increasingly being executed on mobile and embedded platforms due to low latency and better privacy. However, efficient deployment on these platforms is challenging due to the intensive computation and…

Hardware Architecture · Computer Science 2022-06-08 Lei Xun , Bashir M. Al-Hashimi , Jonathon Hare , Geoff V. Merrett

Modern large-scale scientific applications consist of thousands to millions of individual tasks. These tasks involve not only computation but also communication with one another. Typically, the communication pattern between tasks is sparse…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-04-03 Christian Schulz , Henning Woydt

The inference of Neural Networks is usually restricted by the resources (e.g., computing power, memory, bandwidth) on edge devices. In addition to improving the hardware design and deploying efficient models, it is possible to aggregate the…

Machine Learning · Computer Science 2021-11-05 Jun-Liang Lin , Sheng-De Wang

The Hierarchical Inference (HI) paradigm employs a tiered processing: the inference from simple data samples are accepted at the end device, while complex data samples are offloaded to the central servers. HI has recently emerged as an…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-06-17 Adarsh Prasad Behera , Roberto Morabito , Joerg Widmer , Jaya Prakash Champati

Deploying pretrained visual models in real-world environments often suffers from significant performance degradation due to the diversity of testing scenarios. Continuous adaptation of learning models on edge devices via unlabeled data…

Neural and Evolutionary Computing · Computer Science 2026-05-08 Jianming Lv , Chengjun Wang , Depin Liang , Qianli Ma , Wei Chen , Xueqi Cheng

CPU-GPU heterogeneous architectures are now commonly used in a wide variety of computing systems from mobile devices to supercomputers. Maximizing the throughput for multi-programmed workloads on such systems is indispensable as one single…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-05-08 Issa Saba , Eishi Arima , Dai Liu , Martin Schulz

This paper presents an instruction-based coordination architecture for Field-Programmable Gate Array (FPGA)-based systems with multiple high-performance Processing Units (PUs) for accelerating Deep Neural Network (DNN) inference. This…

Hardware Architecture · Computer Science 2026-01-06 Anastasios Petropoulos , Theodore Antonakopoulos

Modern microarchitectures are some of the world's most complex man-made systems. As a consequence, it is increasingly difficult to predict, explain, let alone optimize the performance of software running on such microarchitectures. As a…

Performance · Computer Science 2019-03-06 Andreas Abel , Jan Reineke

With ever-increasing application of machine learning models in various domains such as image classification, speech recognition and synthesis, and health care, designing efficient hardware for these models has gained a lot of popularity.…

Machine Learning · Computer Science 2018-01-22 Mahdi Nazemi , Amir Erfan Eshratifar , Massoud Pedram

In the most popular distributed stream processing frameworks (DSPFs), programs are modeled as a directed acyclic graph. This model allows a DSPF to benefit from the parallelism power of distributed clusters. However, choosing the proper…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-11-03 Hamid Nasiri , Saeed Nasehi , Arman Divband , Maziar Goudarzi