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As Exascale computing becomes a reality, the energy needs of compute nodes in cloud data centers will continue to grow. A common approach to reducing this energy demand is to limit the power consumption of hardware components when workloads…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-08-17 Akhilesh Raj , Swann Perarnau , Aniruddha Gokhale

Sequential information contains short- to long-range dependencies; however, learning long-timescale information has been a challenge for recurrent neural networks. Despite improvements in long short-term memory networks (LSTMs), the…

Machine Learning · Computer Science 2021-05-14 Hsiang-Yun Sherry Chien , Javier S. Turek , Nicole Beckage , Vy A. Vo , Christopher J. Honey , Ted L. Willke

Cutting edge FPGAs are not energy efficient as conventionally presumed to be, and therefore, aggressive power-saving techniques have become imperative. The clock rate of an FPGA-mapped design is set based on worst-case conditions to ensure…

Hardware Architecture · Computer Science 2019-11-19 Behnam Khaleghi , Sahand Salamat , Mohsen Imani , Tajana Rosing

Recurrent Neural Networks (RNNs) are becoming increasingly important for time series-related applications which require efficient and real-time implementations. The recent pruning based work ESE suffers from degradation of…

Machine Learning · Computer Science 2018-03-26 Zhe Li , Shuo Wang , Caiwen Ding , Qinru Qiu , Yanzhi Wang , Yun Liang

As neural networks (NN) are deployed across diverse sectors, their energy demand correspondingly grows. While several prior works have focused on reducing energy consumption during training, the continuous operation of ML-powered systems…

Machine Learning · Computer Science 2024-01-10 Minghao Yan , Hongyi Wang , Shivaram Venkataraman

The rapid emergence of edge computing platforms and large-scale data centers has made power efficiency a primary design constraint, particularly for data-intensive and AI-driven workloads. Field-programmable gate arrays (FPGAs) are…

Hardware Architecture · Computer Science 2026-03-30 Akram Ben Ahmed , Takahiro Hirofuchi , Takaaki Fukai

This paper introduces channel gating, a dynamic, fine-grained, and hardware-efficient pruning scheme to reduce the computation cost for convolutional neural networks (CNNs). Channel gating identifies regions in the features that contribute…

Machine Learning · Computer Science 2019-10-30 Weizhe Hua , Yuan Zhou , Christopher De Sa , Zhiru Zhang , G. Edward Suh

Realizing today's cloud-level artificial intelligence functionalities directly on devices distributed at the edge of the internet calls for edge hardware capable of processing multiple modalities of sensory data (e.g. video, audio) at…

Large language model (LLM) inference performance is increasingly bottlenecked by the memory wall. While GPUs continue to scale raw compute throughput, they struggle to deliver scalable performance for memory bandwidth bound workloads. This…

Hardware Architecture · Computer Science 2026-02-25 Matthew Adiletta , Gu-Yeon Wei , David Brooks

Graph Neural Networks (GNNs) are vital for learning from graph-structured data, enabling applications in network analysis, recommendation systems, and speech analytics. Deploying them on edge devices like client PCs and laptops enhances…

Machine Learning · Computer Science 2025-02-14 Arghadip Das , Shamik Kundu , Arnab Raha , Soumendu Ghosh , Deepak Mathaikutty , Vijay Raghunathan

As the field of quantum computing grows, novel algorithms which take advantage of quantum phenomena need to be developed. As we are currently in the NISQ (noisy intermediate scale quantum) era, quantum algorithm researchers cannot reliably…

Quantum Physics · Physics 2024-11-28 Youssef Moawad , Andrew Brown , René Steijl , Wim Vanderbauwhede

The nanoPU is a new networking-optimized CPU designed to minimize tail latency for RPCs. By bypassing the cache and memory hierarchy, the nanoPU directly places arriving messages into the CPU register file. The wire-to-wire latency through…

Hardware Architecture · Computer Science 2020-10-26 Stephen Ibanez , Alex Mallery , Serhat Arslan , Theo Jepsen , Muhammad Shahbaz , Nick McKeown , Changhoon Kim

In this paper, we propose a novel approach that enhances recurrent neural networks (RNNs) by incorporating path signatures into their gating mechanisms. Our method modifies both Long Short-Term Memory (LSTM) and Gated Recurrent Unit (GRU)…

Machine Learning · Computer Science 2025-02-14 Rémi Genet , Hugo Inzirillo

Phase change memory (PCM) is one of the leading candidates for neuromorphic hardware and has recently matured as a storage class memory. Yet, energy and power consumption remain key challenges for this technology because part of the PCM…

Mesoscale and Nanoscale Physics · Physics 2021-09-20 Keren Stern , Nicolás Wainstein , Yair Keller , Christopher M. Neumann , Eric Pop , Shahar Kvatinsky , Eilam Yalon

Recent advances in multi and many-core processors have led to significant improvements in the performance of scientific computing applications. However, the addition of a large number of complex cores have also increased the overall power…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-02-23 Akash Dutta , Jee Choi , Ali Jannesari

CPU-GPU heterogeneous architectures are now commonly used in a wide variety of computing systems from mobile devices to supercomputers. Maximizing the throughput for multi-programmed workloads on such systems is indispensable as one single…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-05-08 Issa Saba , Eishi Arima , Dai Liu , Martin Schulz

One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at very high speeds and to the fact that in order to support…

Hardware Architecture · Computer Science 2011-11-09 I. Papaefstathiou , T. Orphanoudakis , G. Kornaros , C. Kachris , I. Mavroidis , A. Nikologiannis

Neural Processing Units (NPUs) are key to enabling efficient AI inference in resource-constrained edge environments. While peak tera operations per second (TOPS) is often used to gauge performance, it poorly reflects real-world performance…

Hardware Architecture · Computer Science 2025-09-19 Lennart Bamberg , Filippo Minnella , Roberto Bosio , Fabrizio Ottati , Yuebin Wang , Jongmin Lee , Luciano Lavagno , Adam Fuks

Among hardware accelerators for deep-learning inference, data flow implementations offer low latency and high throughput capabilities. In these architectures, each neuron is mapped to a dedicated hardware unit, making them well-suited for…

Machine Learning · Computer Science 2026-03-10 Tobias Habermann , Michael Mecik , Zhenyu Wang , César David Vera , Martin Kumm , Mario Garrido

While spiking neural networks (SNNs) provide a biologically inspired and energy-efficient computational framework, their robustness and the dynamic advantages inherent to biological neurons remain significantly underutilized owing to…

Neural and Evolutionary Computing · Computer Science 2025-09-04 Qianyi Bai , Haiteng Wang , Qiang Yu