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Bit-level sparsity methods skip ineffectual zero-bit operations and are typically applicable within bit-serial deep learning accelerators. This type of sparsity at the bit-level is especially interesting because it is both orthogonal and…

Machine Learning · Computer Science 2024-09-10 Yuzong Chen , Jian Meng , Jae-sun Seo , Mohamed S. Abdelfattah

Fully realizing the potential of acceleration for Deep Neural Networks (DNNs) requires understanding and leveraging algorithmic properties. This paper builds upon the algorithmic insight that bitwidth of operations in DNNs can be reduced…

Neural and Evolutionary Computing · Computer Science 2018-05-31 Hardik Sharma , Jongse Park , Naveen Suda , Liangzhen Lai , Benson Chau , Joon Kyung Kim , Vikas Chandra , Hadi Esmaeilzadeh

Training on the Edge enables neural networks to learn continuously from new data after deployment on memory-constrained edge devices. Previous work is mostly concerned with reducing the number of model parameters which is only beneficial…

Machine Learning · Computer Science 2021-11-01 Abdelrahman Hosny , Marina Neseem , Sherief Reda

Bit-serial architectures can handle Neural Networks (NNs) with different weight precisions, achieving higher resource efficiency compared with bit-parallel architectures. Besides, the weights contain abundant zero bits owing to the fault…

Hardware Architecture · Computer Science 2023-02-02 Wenhao Sun , Zhiwei Zou , Deng Liu , Wendi Sun , Song Chen , Yi Kang

Compute-in-Memory (CIM) and weight sparsity are two effective techniques to reduce data movement during Neural Network (NN) inference. However, they can hardly be employed in the same accelerator simultaneously because CIM requires…

Hardware Architecture · Computer Science 2025-11-19 Weiping Yang , Shilin Zhou , Hui Xu , Yujiao Nie , Qimin Zhou , Zhiwei Li , Changlin Chen

Developing ultra-low-energy superconducting computing and fault-tolerant quantum computing will require scalable superconducting memory. While conventional superconducting logic-based memory cells have facilitated early demonstrations,…

Bit-level sparsity in quantized deep neural networks (DNNs) offers significant potential for optimizing Multiply-Accumulate (MAC) operations. However, two key challenges still limit its practical exploitation. First, conventional bit-serial…

Hardware Architecture · Computer Science 2025-07-15 Feilong Qiaoyuan , Jihe Wang , Zhiyu Sun , Linying Wu , Yuanhua Xiao , Danghui Wang

Based on the assumption that there exists a neural network that efficiently represents a set of Boolean functions between all binary inputs and outputs, we propose a process for developing and deploying neural networks whose weight…

Machine Learning · Computer Science 2020-02-25 Minje Kim , Paris Smaragdis

Bit-serial Processing-In-Memory (PIM) is an attractive paradigm for accelerator architectures, for parallel workloads such as Deep Learning (DL), because of its capability to achieve massive data parallelism at a low area overhead and…

Hardware Architecture · Computer Science 2023-11-21 Aman Arora , Jian Weng , Siyuan Ma , Tony Nowatzki , Lizy K. John

Deep neural networks have achieved impressive results in computer vision and machine learning. Unfortunately, state-of-the-art networks are extremely compute and memory intensive which makes them unsuitable for mW-devices such as IoT…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-03-15 Renzo Andri , Lukas Cavigelli , Davide Rossi , Luca Benini

Weight pruning in deep neural networks (DNNs) can reduce storage and computation cost, but struggles to bring practical speedup to the model inference time. Tensor-cores can significantly boost the throughput of GPUs on dense computation,…

Distributed, Parallel, and Cluster Computing · Computer Science 2022-03-15 Guyue Huang , Haoran Li , Minghai Qin , Fei Sun , Yufei Ding , Yuan Xie

Emerging resistive random-access memory (ReRAM) has recently been intensively investigated to accelerate the processing of deep neural networks (DNNs). Due to the in-situ computation capability, analog ReRAM crossbars yield significant…

Machine Learning · Computer Science 2019-11-21 Jingyang Zhang , Huanrui Yang , Fan Chen , Yitu Wang , Hai Li

Recurrent Neural Networks (RNNs) are used in state-of-the-art models in domains such as speech recognition, machine translation, and language modelling. Sparsity is a technique to reduce compute and memory requirements of deep learning…

Machine Learning · Computer Science 2017-11-09 Sharan Narang , Eric Undersander , Gregory Diamos

Binary Neural Networks (BNNs) enable efficient deep learning by saving on storage and computational costs. However, as the size of neural networks continues to grow, meeting computational requirements remains a challenge. In this work, we…

Machine Learning · Computer Science 2024-07-18 Matt Gorbett , Hossein Shirazi , Indrakshi Ray

Attention-based large language models (LLMs) have transformed modern AI applications, but the quadratic cost of self-attention imposes significant compute and memory overhead. Dynamic sparsity (DS) attention mitigates this, yet its hardware…

Machine Learning · Computer Science 2025-12-09 Huizheng Wang , Hongbin Wang , Shaojun Wei , Yang Hu , Shouyi Yin

Multi-bit spiking neural networks (SNNs) have recently become a heated research spot, pursuing energy-efficient and high-accurate AI. However, with more bits involved, the associated memory and computation demands escalate to the point…

Neural and Evolutionary Computing · Computer Science 2025-12-02 Xingting Yao , Qinghao Hu , Fei Zhou , Tielong Liu , Gang Li , Peisong Wang , Jian Cheng

Deep Convolutional Neural Networks (CNNs) have become state-of-the art for computer vision and other signal processing tasks due to their superior accuracy. In recent years, large efforts have been made to reduce the computational costs of…

Hardware Architecture · Computer Science 2021-04-13 Mario Fischer , Juergen Wassner

Binary Neural Networks (BNNs) can significantly accelerate the inference time of a neural network by replacing its expensive floating-point arithmetic with bitwise operations. Most existing solutions, however, do not fully optimize data…

Machine Learning · Computer Science 2023-04-04 L. Vorabbi , D. Maltoni , S. Santi

Fault-tolerant deep learning accelerator is the basis for highly reliable deep learning processing and critical to deploy deep learning in safety-critical applications such as avionics and robotics. Since deep learning is known to be…

Hardware Architecture · Computer Science 2023-12-22 Qing Zhang , Cheng Liu , Bo Liu , Haitong Huang , Ying Wang , Huawei Li , Xiaowei Li

Conventional neural accelerators rely on isolated self-sufficient functional units that perform an atomic operation while communicating the results through an operand delivery-aggregation logic. Each single unit processes all the bits of…

Machine Learning · Computer Science 2020-04-14 Soroush Ghodrati , Hardik Sharma , Cliff Young , Nam Sung Kim , Hadi Esmaeilzadeh
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