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Related papers: CXL-GPU: Pushing GPU Memory Boundaries with the In…

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Current HPC systems provide memory resources that are statically configured and tightly coupled with compute nodes. However, workloads on HPC systems are evolving. Diverse workloads lead to a need for configurable memory resources to…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-03-23 Jacob Wahlgren , Maya Gokhale , Ivy B. Peng

The rapid increase in LLM model sizes and the growing demand for long-context inference have made memory a critical bottleneck in GPU-accelerated serving systems. Although high-bandwidth memory (HBM) on GPUs offers fast access, its limited…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-12-01 Xinjun Yang , Qingda Hu , Junru Li , Feifei Li , Yicong Zhu , Yuqi Zhou , Qiuru Lin , Jian Dai , Yang Kong , Jiayu Zhang , Guoqiang Xu , Qiang Liu

Compute Express Link (CXL) switch allows memory extension via PCIe physical layer to address increasing demand for larger memory capacities in data centers. However, CXL attached memory introduces 170ns to 400ns memory latency. This becomes…

Hardware Architecture · Computer Science 2025-03-14 Khan Shaikhul Hadi , Naveed Ul Mustafa , Mark Heinrich , Yan Solihin

The growing prevalence of data-intensive workloads, such as artificial intelligence (AI), machine learning (ML), high-performance computing (HPC), in-memory databases, and real-time analytics, has exposed limitations in conventional memory…

The memory system is a major performance determinant for server processors. Ever-growing core counts and datasets demand higher bandwidth and capacity as well as lower latency from the memory system. To keep up with growing demands,…

Hardware Architecture · Computer Science 2023-05-10 Albert Cho , Anish Saxena , Moinuddin Qureshi , Alexandros Daglis

CXL (Compute Express Link) is an emerging open industry-standard interconnect between processing and memory devices that is expected to revolutionize the way systems are designed. It enables cache-coherent, shared memory pools in a…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-01-27 Gal Assa , Moritz Lumme , Lucas Bürgi , Michal Friedman , Ori Lahav

In our exploration of Composable Memory systems utilizing CXL, we focus on overcoming adoption barriers at Hyperscale, underscored by economic models demonstrating Total Cost of Ownership (TCO). While CXL addresses the pressing memory…

Emerging Technologies · Computer Science 2024-04-05 Angelos Arelakis , Nilesh Shah , Yiannis Nikolakopoulos , Dimitrios Palyvos-Giannas

The widening gap between processor speed and storage latency has made data movement a dominant bottleneck in modern systems. Two lines of storage-layer innovation attempted to close this gap: persistent memory shortened the latency…

Operating Systems · Computer Science 2026-04-06 Yiwei Yang , Yanpeng Hu , Yusheng Zheng , Estabon Ramos , Jianchang Su , Andi Quinn , Wei Zhang

Large-scale AI training and inference require hundreds of gigabytes to terabytes of DRAM with high peak to average utilization ratios, resulting in overprovisioning. In cloud computing, DRAM constitutes a significant share of the cost. Yet,…

Hardware Architecture · Computer Science 2026-05-28 Kaustav Goswami , Maryam Babaie , Hoa Nguyen , Venkatesh Akella , Jason Lowe-Power

Compute eXpress Link (CXL) has emerged as a key enabler of memory disaggregation for future heterogeneous computing systems to expand memory on-demand and improve resource utilization. However, CXL is still in its infancy stage and lacks…

Emerging Technologies · Computer Science 2026-01-13 Yanjing Wang , Lizhou Wu , Wentao Hong , Yang Ou , Zicong Wang , Sunfeng Gao , Jie Zhang , Sheng Ma , Dezun Dong , Xingyun Qi , Mingche Lai , Nong Xiao

Emerging Compute Express Link (CXL) enables cost-efficient memory expansion beyond the local DRAM of processors. While its CXL$.$mem protocol provides minimal latency overhead through an optimized protocol stack, frequent CXL memory…

CXLMemSim is a fast, lightweight simulation framework that enables performance characterization of memory systems based on Compute Express Link (CXL) .mem technology. CXL.mem allows disaggregation and pooling of memory to mitigate memory…

Performance · Computer Science 2025-06-18 Yiwei Yang , Brian Zhao , Yusheng Zheng , Pooneh Safayenikoo , Tanvir Ahmed Khan , Andi Quinn

Pooling PCIe devices across multiple hosts offers a promising solution to mitigate stranded I/O resources, enhance device utilization, address device failures, and reduce total cost of ownership. The only viable option today are PCIe…

Persistent Memory (PM) introduces new opportunities for designing crash-consistent applications without the traditional storage overheads. However, ensuring crash consistency in PM demands intricate knowledge of CPU, cache, and memory…

Emerging Technologies · Computer Science 2025-04-25 João Oliveira , João Gonçalves , Miguel Matos

We propose the design and an implementation of a bulk-parallel external memory priority queue to take advantage of both shared-memory parallelism and high external memory transfer speeds to parallel disks. To achieve higher performance by…

Data Structures and Algorithms · Computer Science 2015-04-03 Timo Bingmann , Thomas Keh , Peter Sanders

Recent Serverless workloads tend to be largescaled/CPU-memory intensive, such as DL, graph applications, that require dynamic memory-to-compute resources provisioning. Meanwhile, recent solutions seek to design page management strategies…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-09-26 Yuze Li , Shunyu Yao

Memory disaggregation is an emerging technology that decouples memory from traditional memory buses, enabling independent scaling of compute and memory. Compute Express Link (CXL), an open-standard interconnect technology, facilitates…

Hardware Architecture · Computer Science 2025-03-27 Yujie Yang , Lingfeng Xiang , Peiran Du , Zhen Lin , Weishu Deng , Ren Wang , Andrey Kudryavtsev , Louis Ko , Hui Lu , Jia Rao

The Compute Express Link (CXL) technology facilitates the extension of CPU memory through byte-addressable SerDes links and cascaded switches, creating complex heterogeneous memory systems where CPU access to various endpoints differs in…

Hardware Architecture · Computer Science 2025-11-06 Yiqi Chen , Xiping Dong , Zhe Zhou , Zhao Wang , Jie Zhang , Guangyu Sun

The advent of Compute Express Link (CXL) enables SSDs to participate in the memory hierarchy as large-capacity, byte-addressable memory devices. These CXL-enabled SSDs (CXL-SSDs) offer a promising new tier between DRAM and traditional…

Hardware Architecture · Computer Science 2025-08-18 Hyunsun Chung , Junhyeok Park , Taewan Noh , Seonghoon Ahn , Kihwan Kim , Ming Zhao , Youngjae Kim

The CXL-based solid-state drive (CXL-SSD) provides a promising approach towards scaling the main memory capacity at low cost. However, the CXL-SSD faces performance challenges due to the long flash access latency and unpredictable events…

Hardware Architecture · Computer Science 2025-01-22 Haoyang Zhang , Yuqi Xue , Yirui Eric Zhou , Shaobo Li , Jian Huang